{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1355C-100BGC","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1355C-100BGC","canonicalUrl":"https://icboms.com/infineon/CY7C1355C-100BGC","factsUrl":"https://icboms.com/api/mcp/products/CY7C1355C-100BGC","rawCanonicalId":null},"summary":{"shortDescription":"Infineon Technologies NoBL™ SRAM, Synchronous SDR, 9Mbit, 256K x 36, 100 MHz, 7.5 ns, 3.135V-3.6V, 0°C-70°C, 119-PBGA, Tray.","salesMarkdown":"## Obsolete — last-time-buy window closed Infineon Technologies has marked the CY7C1355C-100BGC as Obsolete. This means the manufacturer has discontinued production and no last-time-buy window remains open. Sourcing now runs through independent distribution channels — quantities are lot-specific and confirmed at RFQ. ## 256K x 36 at 100 MHz — the pipeline decision This is a 9 Mbit synchronous SRAM organized as 256K words by 36 bits. The 100 MHz clock frequency and 7.5 ns access time set the read/write throughput ceiling — the pipeline depth and output hold time relative to the next clock edge determine whether this part meets the bus timing in a given controller interface. The 36-bit word width suits systems that need parity or ECC bits alongside a 32-bit data path without an extra chip. ## NoBL architecture — why it matters for back-to-back transactions The NoBL (No Bus Latency) series eliminates the dead cycle between read and write operations that conventional synchronous SRAMs require. In a cache-line fill followed by a write-back, the controller can issue a write on the clock edge immediately after the read address — no idle cycle needed. This matters most in systems where memory bandwidth is the bottleneck, such as network packet buffers or DSP scratchpads. ## 119-ball PBGA — footprint and rework considerations Housed in a 119-ball plastic BGA with a 14x22 mm body. The 1.27 mm ball pitch is standard for this density — four-layer board fan-out is straightforward, and the package is reworkable with a typical hot-air profile. ## Supply rails and interface The parallel memory interface uses standard LVTTL I/O levels; no external level translation is needed when the controller also runs at 3.3 V.","metaTitle":"CY7C1355C-100BGC 9Mbit NoBL SRAM, 100 MHz, 119-BGA","metaDescription":"Infineon CY7C1355C-100BGC 9Mbit synchronous SRAM, 100 MHz clock, 7.5 ns access, 256K x 36, 119-PBGA.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Obsolete","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"NoBL™","Package":"Tray","Technology":"SRAM - Synchronous, SDR","Access Time":"7.5 ns","Memory Size":"9Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"119-BGA","Product Status":"Obsolete","Clock Frequency":"100 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"3.135V ~ 3.6V","Base Product Number":"CY7C1355","Memory Organization":"256K x 36","Operating Temperature":"0°C ~ 70°C (TA)","Supplier Device Package":"119-PBGA (14x22)","Write Cycle Time - Word, Page":"-"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":null,"stockQuantity":0,"priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/3c6cabb148834b33323f901bc271483d.pdf","sourceUrl":null},"ai":{"faq":[],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1355C-100BGC","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1355C-100BGC when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-21T02:01:04.067Z","lastPublished":"2026-07-21T02:01:04.067Z","indexable":true}}