{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1355C-100AXC","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1355C-100AXC","canonicalUrl":"https://icboms.com/infineon/CY7C1355C-100AXC","factsUrl":"https://icboms.com/api/mcp/products/CY7C1355C-100AXC","rawCanonicalId":null},"summary":{"shortDescription":"Infineon Technologies NoBL™ SRAM, Synchronous SDR, 9Mbit, 256K x 36, 100 MHz, 7.5 ns, 100-TQFP, Tray.","salesMarkdown":"## 256K x 36 synchronous SRAM — what the 100 MHz clock and 7.5 ns access mean on the bus The CY7C1355C-100AXC is a 9 Mbit synchronous SRAM organized as 256K words by 36 bits. It clocks at 100 MHz and delivers a 7.5 ns access time from clock edge to data valid — this sets the bus turnaround window for the memory controller. The 36-bit wide word matches a 32-bit data bus with parity or ECC bits, or a 36-bit DSP data path, without needing two chips. ## NoBL™ pipeline — dead-cycle elimination on a shared bus This part belongs to the NoBL™ (No Bus Latency) family. The pipeline architecture lets the controller issue a new read or write address on every clock cycle without inserting dead cycles between reads and writes. On a shared memory bus where the master alternates read and write transactions, NoBL™ keeps the data rate at the full 100 MHz instead of dropping to half-rate during direction changes. ## 100-TQFP footprint — rework and board integration Housed in a 100-lead TQFP with a 14x20 mm body (supplier device package 100-TQFP). The 0.5 mm pitch fine-pitch QFP is hand-reworkable with hot air and flux — the leads are exposed, so alignment and solder inspection are straightforward compared to a BGA. Pin 1 is chamfered on the package corner; the orientation mark is unambiguous under a microscope. Infineon lists this part as Obsolete. The 100-TQFP package and 3.3 V synchronous interface are common enough that a functional replacement exists in the same density/speed grade, but a pin-compatible drop-in is not guaranteed without a cross-reference check against the BOM's timing and loading.","metaTitle":"CY7C1355C-100AXC Infineon SRAM, 9Mbit, 100 MHz, 100-TQFP","metaDescription":"CY7C1355C-100AXC synchronous SRAM, 9Mbit (256K x 36), 7.5 ns access, 100 MHz clock, 100-TQFP. Obsolete — sourced to order against RFQ.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Obsolete","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"NoBL™","Package":"Tray","Technology":"SRAM - Synchronous, SDR","Access Time":"7.5 ns","Memory Size":"9Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"100-LQFP","Product Status":"Obsolete","Clock Frequency":"100 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"3.135V ~ 3.6V","Base Product Number":"CY7C1355","Memory Organization":"256K x 36","Operating Temperature":"0°C~70°C(TA)","Supplier Device Package":"100-TQFP (14x20)","Write Cycle Time - Word, Page":"-"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":null,"stockQuantity":0,"priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/ed84243fe66837106fd618dc4170b8ee.pdf","sourceUrl":null},"ai":{"faq":[{"question":"What does the 7.5 ns access time mean for system timing?","answer":"The 7.5 ns is the time from the rising clock edge to data appearing on the output pins. At a 100 MHz clock (10 ns period), the controller has 2.5 ns of setup/hold margin after the access delay before the next clock edge — tight for heavily loaded buses. The 36-bit output bus drives 30 pF per load; adding more than two loads on the same trace erodes the timing margin below the datasheet minimum."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1355C-100AXC","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1355C-100AXC when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-21T02:00:55.724Z","lastPublished":"2026-07-21T02:00:55.724Z","indexable":true}}