{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1354C-200AXI","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1354C-200AXI","canonicalUrl":"https://icboms.com/infineon/CY7C1354C-200AXI","factsUrl":"https://icboms.com/api/mcp/products/CY7C1354C-200AXI","rawCanonicalId":null},"summary":{"shortDescription":"Infineon Technologies NoBL™ synchronous SRAM, 9Mbit (256K x 36), 200 MHz clock, 3.2 ns access, 3.3V supply, industrial temp -40°C to 85°C, 100-TQFP (14x20), tray.","salesMarkdown":"The CY7C1354C-200AXI is a 9 Mbit synchronous SRAM organized as 256K words by 36 bits, part of the Cypress/Infineon NoBL™ (No Bus Latency) series that eliminates dead cycles between read and write operations on the same bus. Rated for a 200 MHz clock frequency with a 3.2 ns access time — the 200 MHz ceiling governs the maximum bus throughput in a pipelined system, while the 3.2 ns access determines the read-to-data-valid latency from the address strobe. Housed in a 100-lead LQFP (also designated 100-TQFP, 14x20 mm body) — a standard 0.5 mm pitch QFP footprint that routes cleanly on a 4-layer PCB with a single ground plane under the package. Available through independent distribution channels; quantities are lot-specific and confirmed at RFQ. No pin-compatible direct replacement exists from the original manufacturer — a board-level redesign would be required to substitute a different synchronous SRAM family.","metaTitle":"Infineon CY7C1354C-200AXI 9Mbit SRAM, 200 MHz, 3.2 ns","metaDescription":"CY7C1354C-200AXI from Infineon Technologies — 9Mbit synchronous SRAM, 256K x 36, 200 MHz clock, 3.2 ns access.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Obsolete","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"NoBL™","Package":"Tray","Technology":"SRAM - Synchronous, SDR","Access Time":"3.2 ns","Memory Size":"9Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"100-LQFP","Product Status":"Obsolete","Clock Frequency":"200 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"3.135V ~ 3.6V","Base Product Number":"CY7C1354","Memory Organization":"256K x 36","Operating Temperature":"-40°C~85°C(TA)","Supplier Device Package":"100-TQFP (14x20)","Write Cycle Time - Word, Page":"-"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$4.3000","priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/8b89357562a3e91f046218f21ff35d82.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/CY7C1354C-200AXI/alternatives.json"},"ai":{"faq":[{"question":"What is the memory organization and bus width of the CY7C1354C-200AXI?","answer":"Organized as 256K words by 36 bits, giving 9 Mbit total density. The 36-bit word width supports 32-bit data plus 4 parity/ECC bits, or a full 36-bit wide data bus for FPGA or ASIC interfaces."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1354C-200AXI","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1354C-200AXI when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-21T02:00:41.597Z","lastPublished":"2026-07-21T02:00:41.597Z","indexable":true}}