{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1352B-100AC","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1352B-100AC","canonicalUrl":"https://icboms.com/infineon/CY7C1352B-100AC","factsUrl":"https://icboms.com/api/mcp/products/CY7C1352B-100AC","rawCanonicalId":null},"summary":{"shortDescription":"Infineon Technologies CY7C1352B-100AC synchronous SDR SRAM, 4.5 Mbit (256K x 18), 100 MHz clock, 5 ns access, parallel interface, 100-TQFP (14x20), 3.135V–3.465V supply, 0°C to 70°C.","salesMarkdown":"The CY7C1352B-100AC: Availability and pricing are lot-specific and confirmed at RFQ — no stock-holding claim is made here. ## 256K x 18 synchronous SDR SRAM — 100 MHz, 5 ns access The CY7C1352B-100AC is a 4.5 Mbit synchronous SRAM organized as 256K words by 18 bits. The 100 MHz clock and 5 ns access time place it in the mid-speed synchronous SRAM class, suited for cache, buffer, and look-up table applications that need deterministic read/write latency without the refresh overhead of DRAM. The parallel memory interface and single-data-rate (SDR) pipeline mean the address is latched on the rising clock edge and data appears after the programmed CAS latency — a familiar flow for designers migrating from asynchronous SRAM to a clocked bus. ## Supply rails and temperature envelope Operates from a 3.135 V to 3.465 V core supply — a narrow 3.3 V ±5 % window that demands a clean rail. The commercial temperature grade (0°C to 70°C) limits this variant to indoor, controlled-environment equipment; the industrial or automotive grades in the same family use different suffix codes. Housed in a 100-lead LQFP (also specified as 100-TQFP, 14x20 mm body). The fine-pitch (0.5 mm) quad flat pack requires careful PCB land pattern design and a controlled soldering profile — standard for this package class.","metaTitle":"CY7C1352B-100AC Infineon SRAM, 4.5Mbit, 100 MHz","metaDescription":"Infineon CY7C1352B-100AC synchronous SDR SRAM, 4.5 Mbit (256K x 18), 100 MHz clock, 5 ns access, 100-TQFP. Obsolete — sourced to order via independent channels.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Obsolete","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"-","Package":"Bag","Technology":"SRAM - Synchronous, SDR","Access Time":"5 ns","Memory Size":"4.5Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"100-LQFP","Product Status":"Obsolete","Clock Frequency":"100 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"3.135V ~ 3.465V","Base Product Number":"CY7C1352","Memory Organization":"256K x 18","Operating Temperature":"0°C~70°C(TA)","Supplier Device Package":"100-TQFP (14x20)","Write Cycle Time - Word, Page":"-"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$3.1400","priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/284cb95364f477a308b6d7ea1959ebe2.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/CY7C1352B-100AC/alternatives.json"},"ai":{"faq":[{"question":"What is the memory organization and clock speed of the CY7C1352B-100AC?","answer":"It is a 4.5 Mbit synchronous SRAM organized as 256K x 18 bits, with a 100 MHz maximum clock frequency and a 5 ns access time."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1352B-100AC","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1352B-100AC when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-21T02:00:09.784Z","lastPublished":"2026-07-21T02:00:09.784Z","indexable":true}}