{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1351F-100AC","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1351F-100AC","canonicalUrl":"https://icboms.com/infineon/CY7C1351F-100AC","factsUrl":"https://icboms.com/api/mcp/products/CY7C1351F-100AC","rawCanonicalId":null},"summary":{"shortDescription":"Infineon (Cypress) CY7C1351F-100AC synchronous SRAM, 4.5Mbit (128K x 36), 100 MHz clock, 8 ns access time, 3.135V-3.6V, 0°C to 70°C, 100-TQFP (14x20 mm), Tray.","salesMarkdown":"## 128K x 36 synchronous SRAM — the 100 MHz bus-fit The CY7C1351F-100AC is a 4.5 Mbit synchronous SRAM organized as 128K words of 36 bits each. The 36-bit word width accommodates 32 data bits plus four parity or ECC bits in a single chip, which simplifies memory controller design for networking and telecom equipment that needs byte-level parity coverage. The 100 MHz clock frequency and 8 ns access time define the bus timing margin: at 100 MHz the cycle time is 10 ns, so the 8 ns access gives a 2 ns window for address-to-data setup before the next rising edge — tight but workable with controlled PCB impedance and matched trace lengths. The single-data-rate (SDR) interface latches addresses on the rising edge only, which halves the pin count versus DDR but limits peak bandwidth to 100 MT/s per chip. If your system sees extended temperature swings or requires AEC-Q100 qualification, this is not the fit. ## Package — 100-TQFP, 14x20 mm body The Tray shipping medium is the factory packaging for this order code. The 100-pin QFP is a common footprint for synchronous SRAMs in this density class, which opens the door to pin-compatible second sourcing — but the obsolete status means any alternate must be qualified independently.","metaTitle":"CY7C1351F-100AC Infineon (Cypress) 4.5Mbit Synchronous SRAM","metaDescription":"CY7C1351F-100AC synchronous SRAM, 128K x 36, 8 ns access time, 100 MHz clock, 100-TQFP.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Obsolete","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"-","Package":"Tray","Technology":"SRAM - Synchronous, SDR","Access Time":"8 ns","Memory Size":"4.5Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"100-LQFP","Product Status":"Obsolete","Clock Frequency":"100 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"3.135V ~ 3.6V","Base Product Number":"CY7C1351","Memory Organization":"128K x 36","Operating Temperature":"0°C~70°C(TA)","Supplier Device Package":"100-TQFP (14x20)","Write Cycle Time - Word, Page":"-"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":null,"stockQuantity":0,"priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/2df07c942b068ed9901e4a0f4dccee0a.pdf","sourceUrl":null},"ai":{"faq":[],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1351F-100AC","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1351F-100AC when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-17T19:50:00.618Z","lastPublished":"2026-07-17T19:50:00.618Z","indexable":true}}