{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1350G-200AXC","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1350G-200AXC","canonicalUrl":"https://icboms.com/infineon/CY7C1350G-200AXC","factsUrl":"https://icboms.com/api/mcp/products/CY7C1350G-200AXC","rawCanonicalId":null},"summary":{"shortDescription":"Infineon NoBL™ CY7C1350G-200AXC synchronous SRAM, 4.5Mbit (128K x 36), 200 MHz clock, 2.8 ns access, parallel interface, 3.135V-3.6V supply, 0°C to 70°C, 100-TQFP.","salesMarkdown":"## 200 MHz synchronous SRAM with NoBL — what the 2.8 ns access buys you The Infineon CY7C1350G-200AXC is a 4.5 Mbit synchronous SRAM organized 128K x 36, built on the NoBL (No Bus Latency) architecture. That means the memory can sustain back-to-back reads and writes on every clock cycle without inserting dead cycles for bus turnaround — a trait that matters when you are feeding a high-throughput datapath like a network processor or a DSP pipeline. The 200 MHz clock rate paired with a 2.8 ns access time gives the system architect a predictable timing budget: the address-to-data valid window is tight enough that you will want to close timing with the board's trace delay accounted for, but the part delivers the full 200 MT/s throughput when the pipeline is kept full. ## 128K x 36 — why the width matters The 36-bit word width is deliberate: it matches a 32-bit data bus plus four parity bits (or ECC syndrome bits) without needing external byte-lane muxing. In a typical FPGA or ASIC cache application, you connect the 36-bit data bus directly to the core logic and use the extra two bits for in-line error detection. The 128K depth at that width means 4.5 Mbits total — enough for a moderate-size lookup table, a trace buffer, or a packet descriptor memory without spilling into a second device. ## Supply and temperature — 3.3 V, commercial range only The 100-pin TQFP (14x20 mm body) is a surface-mount package that reflows with standard lead-free profiles and is inspectable under a microscope, which the rework lab techs appreciate. That said, the broader NoBL family has higher-density siblings (9 Mbit, 250 MHz) if the system outgrows this footprint — but those are different MPNs, not drop-in upgrades. ## Board-level reality — 100-TQFP, 0.5 mm pitch The 100-TQFP package has a 0.5 mm lead pitch. The PCB layout needs a soldermask-defined pad with a 0.25 mm to 0.30 mm pad width and a via-in-pad strategy if the decoupling caps sit on the back side. The supply pins are distributed around the periphery — you will want a 0.1 µF ceramic right at each VDDQ/VSS pair and a 4.7 µF bulk cap within 5 mm of the package. The 3.3 V core supply and the I/O supply share the same rail on this variant, so no separate VDDQ regulator is needed.","metaTitle":"CY7C1350G-200AXC NoBL SRAM, 4.5Mbit, 200 MHz, 2.8 ns","metaDescription":"Infineon CY7C1350G-200AXC synchronous SRAM: 4.5Mbit, 200 MHz clock, 2.8 ns access, 128Kx36, 100-TQFP, 3.3V, active production.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"NoBL™","Package":"Tray","Technology":"SRAM - Synchronous, SDR","Access Time":"2.8 ns","Memory Size":"4.5Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"100-LQFP","Product Status":"Active","Clock Frequency":"200 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"3.135V ~ 3.6V","Base Product Number":"CY7C1350","Memory Organization":"128K x 36","Operating Temperature":"0°C ~ 70°C (TA)","Supplier Device Package":"100-TQFP (14x20)","Write Cycle Time - Word, Page":"-"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$6.0500","priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/1010e2abd040a8dbfb446902223787a6.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/CY7C1350G-200AXC/alternatives.json"},"ai":{"faq":[{"question":"What is the exact access time and clock speed of CY7C1350G-200AXC?","answer":"The access time is 2.8 ns and the maximum clock frequency is 200 MHz. These two numbers together define the timing budget: at 200 MHz the cycle time is 5 ns, and the 2.8 ns access means data is valid 2.8 ns after the clock edge that launches the address, leaving 2.2 ns for setup and hold on the receiving flip-flop."},{"question":"Is CY7C1350G-200AXC a direct replacement for CY7C1350G-200AXI?","answer":"The CY7C1350G-200AXI is the industrial-temperature variant (typically -40°C to +85°C). The CY7C1350G-200AXC is the commercial-temperature variant (0°C to 70°C). They share the same 200 MHz speed grade, 2.8 ns access time, and 100-TQFP package, but the temperature range differs. If your application requires operation below 0°C, the AXI variant is the correct choice."},{"question":"When sourcing CY7C1350G-200AXC, what is the closest functional alternative — CY7C1356C-250AXC?","answer":"The CY7C1356C-250AXC is a higher-density sibling (9 Mbit, 512K x 18) with a 250 MHz clock and the same 2.8 ns access time. It is not a pin-compatible drop-in — the organization and pinout differ (18-bit vs 36-bit word). It is a functional alternative if you need more memory depth at a higher clock rate and can adapt the board layout and bus width."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1350G-200AXC","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1350G-200AXC when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}