{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1338G-117AXC","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1338G-117AXC","canonicalUrl":"https://icboms.com/infineon/CY7C1338G-117AXC","factsUrl":"https://icboms.com/api/mcp/products/CY7C1338G-117AXC","rawCanonicalId":null},"summary":{"shortDescription":"Infineon Technologies CY7C1338G-117AXC synchronous SDR SRAM, 4Mbit (128K x 32), 117 MHz clock, 7.5 ns access, 3.15V–3.6V, 100-TQFP, tray.","salesMarkdown":"## Device identity and synchronous SRAM pipeline The CY7C1338G-117AXC is a 4Mbit synchronous SDR SRAM organized 128K x 32, clocked at 117 MHz with a 7.5 ns access time from the clock edge. The parallel interface and 3.15V to 3.6V supply rail place it in the mid-density synchronous SRAM class, typically used as a cache or buffer in networking, telecom, or DSP pipelines where deterministic read/write latency matters. ## Package and board-fit for 100-TQFP Housed in a 100-TQFP (14x20 mm) per the supplier device package, this surface-mount SRAM requires a 0.50 mm pitch layout — the fine-pitch QFP demands careful solder-paste stencil design and X-ray inspection after reflow to catch bridging on the inner rows. The commercial temperature grade (0°C to 70°C) limits deployment to indoor, temperature-controlled environments — not suitable for extended industrial or automotive ambient ranges without thermal management. ## Obsolete lifecycle — sourcing through independent channels No pin-compatible direct replacement from Infineon exists, so a BOM substitution requires a board spin or a functionally equivalent SRAM from a different family. ## What the 117 MHz clock and 7.5 ns access mean for timing closure The 117 MHz clock rate sets the pipeline cycle — the 7.5 ns access time is the delay from the rising clock edge to valid data on the bus, which must be budgeted into the controller's input setup/hold window. At 117 MHz, the cycle time is about 8.5 ns — the 7.5 ns access leaves roughly 1 ns of margin before the next clock edge, which tightens the PCB trace-length matching and on-die variation tolerance.","metaTitle":"CY7C1338G-117AXC Infineon SRAM, 4Mbit, 117 MHz, 100-TQFP","metaDescription":"CY7C1338G-117AXC Infineon synchronous SDR SRAM, 4Mbit (128K x 32), 117 MHz clock, 7.5 ns access, 100-TQFP. Obsolete — sourced to order against RFQ.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Obsolete","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"-","Package":"Tray","Technology":"SRAM - Synchronous, SDR","Access Time":"7.5 ns","Memory Size":"4Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"100-LQFP","Product Status":"Obsolete","Clock Frequency":"117 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"3.15V ~ 3.6V","Base Product Number":"CY7C1338","Memory Organization":"128K x 32","Operating Temperature":"0°C~70°C(TA)","Supplier Device Package":"100-TQFP (14x20)","Write Cycle Time - Word, Page":"-"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":null,"stockQuantity":0,"priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/e73a6f31b39a0964c598e9443ad2f81a.pdf","sourceUrl":null},"ai":{"faq":[{"question":"What is the memory organization and clock speed of CY7C1338G-117AXC?","answer":"It is a 4Mbit synchronous SDR SRAM organized as 128K x 32, clocked at 117 MHz with a 7.5 ns access time from the clock edge."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1338G-117AXC","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1338G-117AXC when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-21T01:59:28.990Z","lastPublished":"2026-07-21T01:59:28.990Z","indexable":true}}