{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1312CV18-167BZI","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1312CV18-167BZI","canonicalUrl":"https://icboms.com/infineon/CY7C1312CV18-167BZI","factsUrl":"https://icboms.com/api/mcp/products/CY7C1312CV18-167BZI","rawCanonicalId":null},"summary":{"shortDescription":"Infineon Technologies CY7C1312CV18-167BZI, QDR II synchronous SRAM, 18 Mbit (1M x 18), 167 MHz, 1.7V-1.9V, -40°C to 85°C, 165-FBGA (13x15 mm), Tray.","salesMarkdown":"The CY7C1312CV18-167BZI: The 165-FBGA package with a 13x15 mm body and 1.0 mm ball pitch demands a multi-layer PCB with controlled impedance for the QDR II interface traces. Decoupling capacitors should be placed close to each supply ball pair; the 1.7V-1.9V core rail requires low-ESR ceramic caps at both the package perimeter and at the board power entry. The 165-ball array has no center thermal pad; junction-to-board thermal resistance is managed through the signal balls and the board copper plane. ## Memory architecture and timing considerations As a QDR II device, the CY7C1312CV18-167BZI provides separate read and write data ports, each 18 bits wide, allowing simultaneous read and write operations at the full 167 MHz clock rate. The 1M x 18 organization yields 18 Mbit total density, with the 18-bit word width suited for 18-bit DSP datapaths or as a 2-byte-wide buffer with parity. The 167 MHz clock frequency gives a 6 ns cycle time for each port — read and write operations each complete within one clock cycle. Timing closure on the QDR II bus requires matched trace lengths between the controller and the SRAM for all address, data, and control signals, with propagation delays kept within 50 ps skew to meet the setup/hold windows.","metaTitle":"Infineon CY7C1312CV18-167BZI QDR II SRAM, 18 Mbit, 167 MHz","metaDescription":"Obsolete Infineon CY7C1312CV18-167BZI 18 Mbit QDR II synchronous SRAM, 167 MHz, 165-FBGA. Sourced to order against RFQ via independent channels.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Obsolete","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"-","Package":"Tray","Technology":"SRAM - Synchronous, QDR II","Memory Size":"18Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"165-LBGA","Product Status":"Obsolete","Clock Frequency":"167 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"1.7V ~ 1.9V","Base Product Number":"CY7C1312","Memory Organization":"1M x 18","Operating Temperature":"-40°C ~ 85°C (TA)","Supplier Device Package":"165-FBGA (13x15)","Write Cycle Time - Word, Page":"-"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$33.6500","priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/fbada08063fee56eba98088bca25d57d.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/CY7C1312CV18-167BZI/alternatives.json"},"ai":{"faq":[{"question":"What is the memory density and organization of CY7C1312CV18-167BZI?","answer":"It is an 18 Mbit synchronous SRAM organized as 1,048,576 words x 18 bits (1M x 18). The QDR II interface provides separate read and write ports, each 18 bits wide, operating at 167 MHz."},{"question":"What package does CY7C1312CV18-167BZI use?","answer":"The device is supplied in a 165-ball Fine-Pitch Ball Grid Array (FBGA) package measuring 13x15 mm. It is surface-mount and shipped in tray packaging."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1312CV18-167BZI","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1312CV18-167BZI when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-21T01:58:01.434Z","lastPublished":"2026-07-21T01:58:01.434Z","indexable":true}}