{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C131-55JXIT","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C131-55JXIT","canonicalUrl":"https://icboms.com/infineon/CY7C131-55JXIT","factsUrl":"https://icboms.com/api/mcp/products/CY7C131-55JXIT","rawCanonicalId":null},"summary":{"shortDescription":"Infineon CY7C131-55JXIT, SRAM - Dual Port, Asynchronous, 8Kbit (1K x 8), 55 ns access, Parallel interface, 4.5V~5.5V supply, -40°C~85°C, 52-PLCC (19.13x19.13), Tape & Reel.","salesMarkdown":"## Dual-port SRAM for shared-memory handshaking The Infineon CY7C131-55JXIT is an 8Kbit asynchronous dual-port SRAM organized as 1K x 8. It gives two independent processors simultaneous access to a common memory array without bus arbitration logic. No further factory orders or last-time-buy windows are open.","metaTitle":"Infineon CY7C131-55JXIT SRAM Dual Port Asynchronous, 55 ns","metaDescription":"CY7C131-55JXIT 8Kbit dual-port asynchronous SRAM, 55 ns access, -40 to 85°C, 52-PLCC. Obsolete — sourced to order against RFQ. Request quote.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Obsolete","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"-","Package":"Tape & Reel (TR)","Technology":"SRAM - Dual Port, Asynchronous","Access Time":"55 ns","Memory Size":"8Kbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"52-LCC (J-Lead)","Product Status":"Obsolete","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"4.5V ~ 5.5V","Base Product Number":"CY7C131","Memory Organization":"1K x 8","Operating Temperature":"-40°C ~ 85°C (TA)","Supplier Device Package":"52-PLCC (19.13x19.13)","Write Cycle Time - Word, Page":"55ns"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$15.1512","priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/4525bc76605bfaec121d3b7d6a8f362d.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/CY7C131-55JXIT/alternatives.json"},"ai":{"faq":[{"question":"Is CY7C131-55JXIT obsolete?","answer":"Yes, Infineon lists the CY7C131-55JXIT as obsolete. No factory production or last-time-buy remains."},{"question":"What is the replacement for CY7C131-55JXIT?","answer":"The evidence does not list an official successor order code. For a pin-compatible alternative, search the CY7C131 base product family in the same 52-PLCC package — density and speed variants may still be active. We can help cross-reference against your BOM on request."},{"question":"What are the key specifications of CY7C131-55JXIT?","answer":"8Kbit asynchronous dual-port SRAM organized 1K x 8, 55 ns access time, parallel interface, 4.5V to 5.5V supply, -40°C to 85°C operating temperature, in a 52-PLCC package."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C131-55JXIT","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C131-55JXIT when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-17T19:50:00.618Z","lastPublished":"2026-07-17T19:50:00.618Z","indexable":true}}