{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C131-55JXI","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C131-55JXI","canonicalUrl":"https://icboms.com/infineon/CY7C131-55JXI","factsUrl":"https://icboms.com/api/mcp/products/CY7C131-55JXI","rawCanonicalId":null},"summary":{"shortDescription":"Infineon CY7C131-55JXI, Dual-Port Asynchronous SRAM, 8Kbit (1K x 8), 55 ns access time, Parallel interface, 4.5 V to 5.5 V supply, -40°C to 85°C, 52-PLCC, Tube.","salesMarkdown":"## 55 ns dual-port SRAM for asynchronous cross-domain buffering The Infineon CY7C131-55JXI is a 55 ns asynchronous dual-port SRAM organized as 1K x 8 bits, giving 8 Kbit of volatile storage accessible from two independent ports. The 52-lead PLCC package with J-leads (52-PLCC, 19.13 mm square body) is a surface-mount form factor that typically requires a PLCC socket for prototyping or a reflow profile tuned for J-lead solder joints. The J-lead footprint offers good visual inspectability after soldering, unlike a BGA. Infineon lists the CY7C131-55JXI as obsolete. New designs should migrate to a current-production dual-port SRAM or to a different dual-port memory architecture.","metaTitle":"Infineon CY7C131-55JXI Dual-Port SRAM, 8Kbit, 55 ns, 52-PLCC","metaDescription":"Infineon CY7C131-55JXI asynchronous dual-port SRAM, 8Kbit (1K x 8), 55 ns access time, 4.5V-5.5V supply, -40°C to 85°C, 52-PLCC.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Obsolete","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"-","Package":"Tube","Technology":"SRAM - Dual Port, Asynchronous","Access Time":"55 ns","Memory Size":"8Kbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"52-LCC (J-Lead)","Product Status":"Obsolete","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"4.5V ~ 5.5V","Base Product Number":"CY7C131","Memory Organization":"1K x 8","Operating Temperature":"-40°C~85°C(TA)","Supplier Device Package":"52-PLCC (19.13x19.13)","Write Cycle Time - Word, Page":"55ns"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":null,"priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/fddcec30d8718da2846811f345189234.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/CY7C131-55JXI/alternatives.json"},"ai":{"faq":[{"question":"What is the access time of CY7C131-55JXI?","answer":"The access time is 55 ns, which defines the maximum bus clock rate (roughly 18 MHz without wait states) and the read/write cycle timing margin for your design."},{"question":"Where can I buy CY7C131-55JXI?","answer":"Submit an RFQ to confirm current availability and pricing — each lot is quoted to order."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C131-55JXI","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C131-55JXI when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-17T19:50:00.618Z","lastPublished":"2026-07-17T19:50:00.618Z","indexable":true}}