{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C131-55JXCT","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C131-55JXCT","canonicalUrl":"https://icboms.com/infineon/CY7C131-55JXCT","factsUrl":"https://icboms.com/api/mcp/products/CY7C131-55JXCT","rawCanonicalId":null},"summary":{"shortDescription":"Infineon Technologies CY7C131-55JXCT dual-port asynchronous SRAM, 8Kbit (1K x 8), 55 ns access time, 4.5V to 5.5V supply, 52-PLCC, Tape & Reel.","salesMarkdown":"## 8Kbit dual-port SRAM — 55 ns access time The CY7C131-55JXCT: Organized as 1K x 8, this dual-port asynchronous SRAM allows simultaneous read/write access from two independent ports — useful for shared-memory buffering between processors or between a processor and an FPGA. 55 ns access time and 55 ns write cycle time set the bus timing floor. In a shared-memory arbitration scheme, the port-to-port handshake must accommodate this delay to avoid data contention. Operates from a single 4.5V to 5.5V supply — a legacy 5V rail, common in industrial and telecom backplanes where the CY7C131 series was originally designed in. ## 52-PLCC package — board-fit considerations Supplied in a 52-lead PLCC (J-lead) package, supplier device package 52-PLCC (19.13x19.13 mm). The J-lead footprint is surface-mount but requires a PLCC socket or a reflow profile compatible with the lead pitch. Tape & Reel packaging indicates it was originally intended for automated pick-and-place assembly. For prototype or low-volume builds, verify the PLCC socket availability against the 52-position JEDEC footprint. Commercial temperature range (0°C to 70°C) — suitable for indoor equipment, not extended or industrial thermal environments.","metaTitle":"CY7C131-55JXCT Infineon 8Kbit SRAM, 55 ns, 52-PLCC","metaDescription":"Infineon CY7C131-55JXCT 8Kbit dual-port asynchronous SRAM, 55 ns access time, 4.5-5.5V, 52-PLCC. Obsolete — sourced to order against RFQ.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Obsolete","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"-","Package":"Tape & Reel (TR)","Technology":"SRAM - Dual Port, Asynchronous","Access Time":"55 ns","Memory Size":"8Kbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"52-LCC (J-Lead)","Product Status":"Obsolete","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"4.5V ~ 5.5V","Base Product Number":"CY7C131","Memory Organization":"1K x 8","Operating Temperature":"0°C ~ 70°C (TA)","Supplier Device Package":"52-PLCC (19.13x19.13)","Write Cycle Time - Word, Page":"55ns"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":null,"stockQuantity":0,"priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/4525bc76605bfaec121d3b7d6a8f362d.pdf","sourceUrl":null},"ai":{"faq":[{"question":"What is the memory size and organization of the CY7C131-55JXCT?","answer":"8Kbit organized as 1K x 8. It is a dual-port asynchronous SRAM, meaning two independent ports can access the memory array simultaneously."},{"question":"What package does the CY7C131-55JXCT use?","answer":"52-lead PLCC (J-lead), supplier device package 52-PLCC (19.13x19.13 mm). Supplied in Tape & Reel."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C131-55JXCT","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C131-55JXCT when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-21T01:58:25.540Z","lastPublished":"2026-07-21T01:58:25.540Z","indexable":true}}