{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1265KV18-400BZXC","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1265KV18-400BZXC","canonicalUrl":"https://icboms.com/infineon/CY7C1265KV18-400BZXC","factsUrl":"https://icboms.com/api/mcp/products/CY7C1265KV18-400BZXC","rawCanonicalId":null},"summary":{"shortDescription":"Infineon (Cypress) CY7C1265KV18-400BZXC, 36 Mbit Synchronous QDR II+ SRAM, 400 MHz clock, 1.7–1.9 V supply, 1M x 36 organization, 165-LBGA (13×15) Tray, 0°C to 70°C.","salesMarkdown":"The Infineon (Cypress) CY7C1265KV18-400BZXC is a 36 Mbit synchronous QDR II+ SRAM organized as 1M x 36, clocked at 400 MHz. The part comes in a 165-LBGA (13x15 mm) package for surface-mount assembly. QDR II+ architecture delivers separate read and write data ports, eliminating the bus-turnaround dead cycles that conventional SRAMs incur. At 400 MHz the part sustains back-to-back read and write transactions at full clock rate — the kind of throughput a network line card or high-end telecom buffer demands. The 400 MHz clock rate translates to a 2.5 ns cycle time. On a QDR II+ bus, each clock edge can launch a data transfer, so the effective data rate per pin is 800 Mbps (double-data-rate on both read and write ports). That bandwidth is what makes this part a fit for packet buffers and lookup tables in 10 GbE and OTN equipment where the SRAM must keep up with the line rate without inserting wait states. ## Temperature grade: indoor equipment only This SRAM belongs in a climate-controlled rack, not an outdoor cabinet or an engine bay. If the board sees -40°C or +85°C, this part will not meet the operating spec. ## Lifecycle reality: obsolete, sourced through independent channels Infineon lists this part as obsolete. No factory lead time applies; the part is sourced from inventory held by distributors and brokers who carry legacy Cypress SRAM.","metaTitle":"CY7C1265KV18-400BZXC Infineon 36Mbit QDR II+ SRAM, 400 MHz","metaDescription":"Infineon (Cypress) CY7C1265KV18-400BZXC 36Mbit Synchronous QDR II+ SRAM, 400 MHz clock, 1M x 36, 165-LBGA, 0°C to 70°C.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Obsolete","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"-","Package":"Tray","Technology":"SRAM - Synchronous, QDR II+","Memory Size":"36Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"165-LBGA","Product Status":"Obsolete","Clock Frequency":"400 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"1.7V ~ 1.9V","Base Product Number":"CY7C1265","Memory Organization":"1M x 36","Operating Temperature":"0°C ~ 70°C (TA)","Supplier Device Package":"165-FBGA (13x15)","Write Cycle Time - Word, Page":"-"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":null,"stockQuantity":0,"priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/277b6dff6a1b6061a2b90de843d6cc80.pdf","sourceUrl":null},"ai":{"faq":[{"question":"Is CY7C1265KV18-400BZXC obsolete?","answer":"Yes, Infineon lists this part as obsolete. There is no factory production or lead time; supply comes from surplus and new-old-stock inventory held by independent distributors."},{"question":"What is the replacement for CY7C1265KV18-400BZXC?","answer":"The QDR II+ family has been through product-line transitions; a pin-compatible drop-in replacement from the same manufacturer is not confirmed. For a design that must stay with the 165-ball BGA footprint and 400 MHz speed grade, the practical path is sourcing the original part through independent channels."},{"question":"What package does CY7C1265KV18-400BZXC use?","answer":"It ships in a 165-LBGA (13x15 mm) package, also described as 165-FBGA. The supplier device package is 165-FBGA (13x15). Mounting is surface mount."},{"question":"Is CY7C1265KV18-400BZXC compatible with QDR II+ interface?","answer":"Yes, the memory technology is SRAM - Synchronous, QDR II+. The QDR II+ architecture provides separate read and write data ports for full-rate back-to-back transactions without bus-turnaround dead cycles."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1265KV18-400BZXC","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1265KV18-400BZXC when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-17T19:50:00.618Z","lastPublished":"2026-07-17T19:50:00.618Z","indexable":true}}