{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1061GE30-10ZSXIT","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1061GE30-10ZSXIT","canonicalUrl":"https://icboms.com/infineon/CY7C1061GE30-10ZSXIT","factsUrl":"https://icboms.com/api/mcp/products/CY7C1061GE30-10ZSXIT","rawCanonicalId":null},"summary":{"shortDescription":"Infineon CY7C1061GE30-10ZSXIT, 16Mbit asynchronous SRAM, 10 ns access time, 1M x 16 organization, 2.2–3.6V supply, 54-TSOP II (Tape & Reel), -40 to 85 °C.","salesMarkdown":"## 10 ns access time — timing margin for the bus The spec record flags this part with an EOL-hot lifecycle stage, while the lifecycle field lists it as Active. This discrepancy suggests a transition phase. This is a standard asynchronous SRAM — no clock, no burst mode, no DDR interface. The control pins are chip enable, output enable, and write enable. The 10 ns write cycle time means a single 10 ns pulse on write enable latches the data. For applications that need back-to-back reads and writes without bus-turnaround penalties, this part delivers because the asynchronous interface has no dead cycles between read and write transitions.","metaTitle":"Infineon CY7C1061GE30-10ZSXIT 16Mbit Async SRAM, 10 ns","metaDescription":"Infineon CY7C1061GE30-10ZSXIT 16Mbit asynchronous SRAM, 10 ns access time, 1M x 16, 2.2-3.6V, -40 to 85°C, 54-TSOP II. Sourced to order against RFQ.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"-","Package":"Tape & Reel (TR)","Technology":"SRAM - Asynchronous","Access Time":"10 ns","Memory Size":"16Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"54-TSOP (0.400\\\", 10.16mm Width)","Product Status":"Active","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"2.2V ~ 3.6V","Base Product Number":"CY7C1061","Memory Organization":"1M x 16","Operating Temperature":"-40°C ~ 85°C (TA)","Supplier Device Package":"54-TSOP II","Write Cycle Time - Word, Page":"10ns"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$27.5000","priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/4341c3411ca6312d176c3d75e3399f9d.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/CY7C1061GE30-10ZSXIT/alternatives.json"},"ai":{"faq":[{"question":"What is the access time of CY7C1061GE30-10ZSXIT?","answer":"The access time is 10 ns for both read and write cycles, specified at the full supply range and temperature grade."},{"question":"What package is CY7C1061GE30-10ZSXIT available in?","answer":"It comes in a 54-TSOP II package (0.400-inch body, 10.16 mm width), supplied on Tape & Reel for automated assembly."},{"question":"What is the memory organization of CY7C1061GE30-10ZSXIT?","answer":"The memory is organized as 1M words by 16 bits (1M x 16), giving a total of 16Mbit."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1061GE30-10ZSXIT","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1061GE30-10ZSXIT when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}