{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1061GE-10ZXI","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1061GE-10ZXI","canonicalUrl":"https://icboms.com/infineon/CY7C1061GE-10ZXI","factsUrl":"https://icboms.com/api/mcp/products/CY7C1061GE-10ZXI","rawCanonicalId":null},"summary":{"shortDescription":"Infineon CY7C1061GE-10ZXI, 16Mbit Asynchronous SRAM, 1M x 16, 10 ns Access Time, Parallel Interface, 4.5V-5.5V Supply, -40°C to 85°C, 54-TSOP II, Tray.","salesMarkdown":"## 10 ns asynchronous SRAM — bus timing and memory sizing This part is typically used in networking equipment, industrial controllers, and test instrumentation where fast, deterministic read/write cycles are needed on a legacy 5V bus. ## 10 ns access time — timing margin for the memory bus For a system clocked at 100 MHz, that leaves roughly 10 ns of setup margin before the next clock edge — enough for a single-cycle read if the controller's output hold and trace delay are managed. ## 1M x 16 organization — bus width match The 1M x 16 organization means the part presents a 16-bit data bus. If your processor or FPGA memory controller expects a 16-bit word, this is a direct fit. For a 32-bit bus you need two devices in parallel, with the address and control lines shared and the chip selects gated by the upper address bits. ## Industrial temperature range and 5V supply If you are on a 3.3V bus, look at the CY7C1061G33 series instead. Housed in a 54-TSOP II (0.400\" body width, 10.16 mm), this is a surface-mount package with JEDEC-standard footprint. The 0.8 mm pin pitch is fine for hand assembly but benefits from a stencil and reflow profile. Listed as Active with no last-time-buy notice. That means Infineon is still manufacturing this part, and the normal supply chain is open.","metaTitle":"CY7C1061GE-10ZXI 16Mbit Async SRAM, 10 ns Access, 54-TSOP II","metaDescription":"Infineon CY7C1061GE-10ZXI 16Mbit asynchronous SRAM, 1M x 16 organization, 10 ns access time, 4.5V-5.5V supply, -40°C to 85°C. Active lifecycle.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"-","Package":"Tray","Technology":"SRAM - Asynchronous","Access Time":"10 ns","Memory Size":"16Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"54-TSOP (0.400\\\", 10.16mm Width)","Product Status":"Active","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"4.5V ~ 5.5V","Base Product Number":"CY7C1061","Memory Organization":"1M x 16","Operating Temperature":"-40°C~85°C(TA)","Supplier Device Package":"54-TSOP II","Write Cycle Time - Word, Page":"10ns"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$38.5000","priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/4341c3411ca6312d176c3d75e3399f9d.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/CY7C1061GE-10ZXI/alternatives.json"},"ai":{"faq":[{"question":"Is CY7C1061GE-10ZXI obsolete?","answer":"No. The lifecycle status is Active, meaning Infineon continues to manufacture it."},{"question":"What is the access time of CY7C1061GE-10ZXI?","answer":"The access time is 10 ns for both read and write cycles."},{"question":"What package is CY7C1061GE-10ZXI?","answer":"It comes in a 54-TSOP II (0.400\" body width, 10.16 mm), surface-mount, with a JEDEC-standard footprint. The supplier device package is 54-TSOP II."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1061GE-10ZXI","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1061GE-10ZXI when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}