{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1061G30-10ZXET","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1061G30-10ZXET","canonicalUrl":"https://icboms.com/infineon/CY7C1061G30-10ZXET","factsUrl":"https://icboms.com/api/mcp/products/CY7C1061G30-10ZXET","rawCanonicalId":null},"summary":{"shortDescription":"Infineon Technologies CY7C1061G30-10ZXET, asynchronous SRAM, 16Mbit (1M x 16), 10 ns access time, 2.2V-3.6V supply, 48-TSOP I, Tape & Reel, -40°C to 85°C.","salesMarkdown":"## 16-Mbit asynchronous SRAM in a 48-TSOP I footprint The Infineon CY7C1061G30-10ZXET is a 16 Mbit asynchronous SRAM organized 1M x 16, with a 10 ns access time that sets the bus cycle ceiling for the memory controller. Housed in a 48-TSOP I (0.724\" body width), this surface-mount package routes 48 pins on a 0.50 mm pitch — the same footprint as the industry-standard TSOP I pinout, so it drops onto existing board layouts without a spin.","metaTitle":"Infineon CY7C1061G30-10ZXET Async SRAM, 16Mbit, 10 ns","metaDescription":"Infineon CY7C1061G30-10ZXET 16Mbit asynchronous SRAM, 1M x 16, 10 ns access time, 2.2V-3.6V, -40°C to 85°C, 48-TSOP I. Active production, sourced to order.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"title":"CY7C1061G30-10ZXET","Package":"Tape & Reel (TR)","Technology":"SRAM - Asynchronous","Access Time":"10 ns","Memory Size":"16Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"48-TFSOP (0.724\\\", 18.40mm Width)","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"2.2V ~ 3.6V","Base Product Number":"CY7C1061","Memory Organization":"1M x 16","Operating Temperature":"-40°C ~ 85°C (TA)","Supplier Device Package":"48-TSOP I","Write Cycle Time - Word, Page":"10ns"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$35.7500","priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/4b93c3469ea1fc2946e8e709077abfe8.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/CY7C1061G30-10ZXET/alternatives.json"},"ai":{"faq":[{"question":"What is the memory organization of the CY7C1061G30-10ZXET?","answer":"It is organized as 1M words by 16 bits (1M x 16), giving a total of 16 Mbit of storage. The 16-bit-wide data bus matches processors and FPGAs with a 16-bit external memory interface without needing byte-lane muxing."},{"question":"What is the access time and write cycle time for this SRAM?","answer":"The access time is 10 ns, and the write cycle time (word, page mode) is also 10 ns. This means the memory can complete a read or write operation every 10 ns, corresponding to a 100 MHz bus cycle if the controller can sustain back-to-back accesses without wait states."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1061G30-10ZXET","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1061G30-10ZXET when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}