{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1061G-10ZSXI","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1061G-10ZSXI","canonicalUrl":"https://icboms.com/infineon/CY7C1061G-10ZSXI","factsUrl":"https://icboms.com/api/mcp/products/CY7C1061G-10ZSXI","rawCanonicalId":null},"summary":{"shortDescription":"Infineon Technologies CY7C1061G-10ZSXI, asynchronous SRAM, 16Mbit (1M x 16), 10 ns access time, 4.5V–5.5V supply, 54-TSOP II surface-mount, -40°C to 85°C.","salesMarkdown":"## 16Mbit asynchronous SRAM, 10 ns access — BOM-fit note The CY7C1061G-10ZSXI: This parallel-interface volatile memory operates from a single 4.5V to 5.5V supply rail, making it a direct fit for legacy 5V-tolerant bus designs or mixed-voltage systems where the SRAM sits on its own regulated 5V plane. The 10 ns access time means the memory can keep pace with a 50 MHz bus without wait states, provided the controller's output hold time and the board trace delay budget are within the SRAM's setup window. ## Active lifecycle — no end-of-life watch needed Infineon lists the CY7C1061G-10ZSXI as Active (current production). For a BOM line that depends on this exact Cypress-origin SRAM, the supply risk is low — the part is still a standard catalog item, not a phase-out candidate. ## Supply rails and temperature grade — what they mean for the design The 4.5V–5.5V supply range is a full 5V ±10% tolerance — the SRAM can run on a 5.0V rail without an external LDO, but it will not operate on a 3.3V-only bus. If the rest of the board is 3.3V, a level translator on the address/data bus is required, and the SRAM needs its own 5V supply or a boost converter. The 54-TSOP II package has an exposed paddle on the bottom — a thermal via array under the paddle to a ground plane improves heat spreading when the ambient cycles near the 85°C ceiling.","metaTitle":"CY7C1061G-10ZSXI Infineon 16Mbit Async SRAM, 10ns","metaDescription":"CY7C1061G-10ZSXI Infineon 16Mbit asynchronous SRAM, 1M x 16, 10ns access, 4.5V-5.5V, -40°C to 85°C, 54-TSOP II. Active production, sourced to order.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"-","Package":"Tray","Technology":"SRAM - Asynchronous","Access Time":"10 ns","Memory Size":"16Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"54-TSOP (0.400\\\", 10.16mm Width)","Product Status":"Active","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"4.5V ~ 5.5V","Base Product Number":"CY7C1061","Memory Organization":"1M x 16","Operating Temperature":"-40°C~85°C(TA)","Supplier Device Package":"54-TSOP II","Write Cycle Time - Word, Page":"10ns"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$38.5000","priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/4341c3411ca6312d176c3d75e3399f9d.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/CY7C1061G-10ZSXI/alternatives.json"},"ai":{"faq":[{"question":"What is the memory organization and access time of CY7C1061G-10ZSXI?","answer":"It is organized as 1M x 16 bits (16Mbit total) with a 10 ns access time and a 10 ns write cycle time (word, page). The parallel interface operates from a 4.5V to 5.5V supply."},{"question":"What package does CY7C1061G-10ZSXI use?","answer":"It is supplied in a 54-TSOP II surface-mount package (0.400-inch body width, 10.16 mm) on tray."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1061G-10ZSXI","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1061G-10ZSXI when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}