{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1061AV33-10BAXI","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1061AV33-10BAXI","canonicalUrl":"https://icboms.com/infineon/CY7C1061AV33-10BAXI","factsUrl":"https://icboms.com/api/mcp/products/CY7C1061AV33-10BAXI","rawCanonicalId":null},"summary":{"shortDescription":"Infineon CY7C1061AV33-10BAXI, 16Mbit asynchronous SRAM, 1M x 16 organization, 10 ns access time, 3V to 3.6V supply, -40°C to 85°C industrial temp, 60-TFBGA package.","salesMarkdown":"The Infineon CY7C1061AV33-10BAXI is a 16Mbit asynchronous SRAM organized 1M x 16, in a 60-TFBGA package. This is a volatile memory — data is lost at power-down. The asynchronous interface means no clock to route: address and control signals latch on the falling edge of chip enable or write enable, making it a straightforward drop-in for legacy bus designs or FPGA block RAM expansion. Infineon (formerly Cypress) has ended production — no last-time-buy window remains open through the factory channel. ## 60-FBGA footprint — layout and rework notes The PCB layout engineer needs a four-layer minimum with microvia capability or at least via-in-pad for the inner balls. Decoupling calls for one 100 nF ceramic per supply ball pair, placed within 2 mm of the ball, plus a 4.7 µF bulk cap on the 3.3V plane. The 10 ns write cycle time (word, page) matches the read access — no asymmetry penalty when the bus alternates read/write cycles at full speed. The write enable timing relative to chip enable is the critical path for the firmware bring-up engineer to verify in the first memory test routine.","metaTitle":"Infineon CY7C1061AV33-10BAXI 16Mbit Async SRAM, 10ns","metaDescription":"Infineon CY7C1061AV33-10BAXI 16Mbit asynchronous SRAM, 1Mx16 organization, 10ns access time, 3V-3.6V, -40 to 85°C, 60-FBGA.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Obsolete","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"-","Package":"Tray","Technology":"SRAM - Asynchronous","Access Time":"10 ns","Memory Size":"16Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"60-TFBGA","Product Status":"Obsolete","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"3V ~ 3.6V","Base Product Number":"CY7C1061","Memory Organization":"1M x 16","Operating Temperature":"-40°C ~ 85°C (TA)","Supplier Device Package":"60-FBGA (8x20)","Write Cycle Time - Word, Page":"10ns"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":null,"stockQuantity":0,"priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/ab2c4095472569df4bda0514f466534b.pdf","sourceUrl":null},"ai":{"faq":[{"question":"Is CY7C1061AV33-10BAXI obsolete?","answer":"Yes, the CY7C1061AV33-10BAXI carries an Obsolete lifecycle status. Infineon has discontinued production with no active last-time-buy window through the factory channel. Supply is limited to existing surplus and new-old-stock inventory in the independent market."},{"question":"Can I use CY7C1061AV33-10BAXI in a 3.3V system?","answer":"Yes. No level translation is needed for the parallel interface if the bus master also runs at 3.3V."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1061AV33-10BAXI","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1061AV33-10BAXI when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-17T19:50:00.618Z","lastPublished":"2026-07-17T19:50:00.618Z","indexable":true}}