{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C1011CV33-10ZSXAT","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C1011CV33-10ZSXAT","canonicalUrl":"https://icboms.com/infineon/CY7C1011CV33-10ZSXAT","factsUrl":"https://icboms.com/api/mcp/products/CY7C1011CV33-10ZSXAT","rawCanonicalId":null},"summary":{"shortDescription":"Infineon Technologies CY7C1011CV33-10ZSXAT asynchronous SRAM, 2Mbit, 128K x 16 organization, 10 ns access time, 3V to 3.6V supply, -40°C to +85°C, 44-TSOP II, Tape & Reel.","salesMarkdown":"## 128K x 16 asynchronous SRAM — 10 ns access, 3.3 V core The CY7C1011CV33-10ZSXAT is a 2 Mbit asynchronous SRAM organized as 128K words by 16 bits. The parallel interface and 10 ns access time place it in the fast-page SRAM class, suitable for cache, buffer, or scratchpad memory in embedded systems where deterministic read/write latency matters more than serial-bus throughput. ## 10 ns access — timing margin in the memory bus Both the address-to-data access time and the write cycle time are specified at 10 ns. For a 100 MHz bus clock with a 10 ns period, this SRAM leaves zero margin for address-to-data setup in a single-cycle read — the controller must insert a wait state or use a pipelined access scheme. At 66 MHz (15 ns period), the 10 ns access provides 5 ns of timing slack before the data latch edge. The write cycle time of 10 ns means the minimum write pulse width is also 10 ns. The controller's write strobe must meet this minimum; a shorter pulse risks incomplete data capture, especially at the temperature extremes where the SRAM's internal timing shifts. ## 44-TSOP II — board integration and rework The 10.16 mm width fits standard SOIC-44 footprints, but the TSOP II body is thinner — verify the solder-paste stencil aperture against the land pattern to avoid bridging on the fine-pitch leads. Supplied in Tape & Reel (TR), the part is ready for pick-and-place assembly in volume production. The reel quantity is not specified here, but TSOP II reels typically carry 1,000 or 2,000 units per reel depending on tape width. ## Active lifecycle — sourcing posture Infineon lists the CY7C1011CV33-10ZSXAT as Active.","metaTitle":"CY7C1011CV33-10ZSXAT Infineon 2Mbit Async SRAM, 10 ns","metaDescription":"Infineon CY7C1011CV33-10ZSXAT 2Mbit asynchronous SRAM, 10 ns access, 128K x 16, 3V-3.6V, -40°C to +85°C, 44-TSOP II. Active production, sourced to order.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"-","Package":"Tape & Reel (TR)","Technology":"SRAM - Asynchronous","Access Time":"10 ns","Memory Size":"2Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"44-TSOP (0.400\\\", 10.16mm Width)","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"3V ~ 3.6V","Base Product Number":"CY7C1011","Memory Organization":"128K x 16","Operating Temperature":"-40°C ~ 85°C (TA)","Supplier Device Package":"44-TSOP II","Write Cycle Time - Word, Page":"10ns"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":null,"stockQuantity":0,"priceTiers":null},"links":{"datasheetUrl":null,"sourceUrl":null},"ai":{"faq":[],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C1011CV33-10ZSXAT","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C1011CV33-10ZSXAT when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}