{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C09189-9AC","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C09189-9AC","canonicalUrl":"https://icboms.com/infineon/CY7C09189-9AC","factsUrl":"https://icboms.com/api/mcp/products/CY7C09189-9AC","rawCanonicalId":null},"summary":{"shortDescription":"Cypress CY7C09189-9AC, 576Kbit Synchronous Dual-Port SRAM, 64K x 9 organization, 9 ns access time, 67 MHz clock, Parallel interface, 4.5V~5.5V supply, 0°C~70°C, 100-TQFP (14x14), Tray.","salesMarkdown":"## 576Kbit synchronous dual-port SRAM — 9 ns access, 67 MHz arbitration The Cypress CY7C09189-9AC is a 576Kbit synchronous dual-port SRAM organized as 64K x 9 bits. It provides two independent ports with separate address, data, and control lines, allowing simultaneous read/write access from two bus masters or processors. The 9 ns access time and 67 MHz clock frequency support high-speed arbitration in multiprocessor or shared-memory systems without dead cycles. ## 9 ns access time — timing margin for dual-port arbitration In a synchronous dual-port design, this rating directly affects the timing closure for read/write cycles when both ports contend for the same memory location. A 9 ns window leaves comfortable margin for a 67 MHz clock period (14.9 ns), provided board traces are kept short and decoupling is adequate. The synchronous architecture eliminates the bus-turnaround dead cycles typical of asynchronous dual-port SRAM, so back-to-back throughput can approach the clock rate. ## Obsolete — last-time-buy and sourcing reality The CY7C09189-9AC is officially obsolete per the manufacturer's lifecycle status. This is not a part to qualify into a new design; it is a legacy fill for existing boards.","metaTitle":"CY7C09189-9AC 576Kbit Synchronous Dual-Port SRAM, 9 ns","metaDescription":"CY7C09189-9AC is an obsolete 576Kbit synchronous dual-port SRAM with 9 ns access time, 67 MHz clock, 64K x 9 organization, 100-TQFP.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Obsolete","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"-","Package":"Tray","Technology":"SRAM - Dual Port, Synchronous","Access Time":"9 ns","Memory Size":"576Kbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"100-LQFP","Product Status":"Obsolete","Clock Frequency":"67 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"4.5V ~ 5.5V","Base Product Number":"CY7C09189","Memory Organization":"64K x 9","Operating Temperature":"0°C~70°C(TA)","Supplier Device Package":"100-TQFP (14x14)","Write Cycle Time - Word, Page":"-"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":null,"stockQuantity":0,"priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/e66cb47ae30cedf2482b1c1f01f6426c.pdf","sourceUrl":null},"ai":{"faq":[{"question":"What is the access time of CY7C09189-9AC?","answer":"The access time is 9 ns. This is the time from address assertion to valid data output on either port, and it is the key timing parameter for bus arbitration in a dual-port system."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C09189-9AC","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C09189-9AC when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-17T19:50:00.618Z","lastPublished":"2026-07-17T19:50:00.618Z","indexable":true}}