{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C037V-15AXC","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C037V-15AXC","canonicalUrl":"https://icboms.com/infineon/CY7C037V-15AXC","factsUrl":"https://icboms.com/api/mcp/products/CY7C037V-15AXC","rawCanonicalId":null},"summary":{"shortDescription":"Infineon Technologies CY7C037V-15AXC dual-port asynchronous SRAM, 576Kbit (32K x 18), 15 ns access time, 3V–3.6V supply, 100-TQFP (14x14), surface mount.","salesMarkdown":"## 576Kbit dual-port SRAM — 15 ns asynchronous access The CY7C037V-15AXC is a 576Kbit dual-port asynchronous SRAM organized 32K x 18, offering simultaneous independent access from two ports without arbitration logic on the memory array itself. Access time is 15 ns, and the write cycle time matches at 15 ns for word or page operations — this sets the bus turnaround floor for a shared-memory interface between two controllers or a controller and an FPGA. Supply voltage spans 3V to 3.6V, with a commercial temperature range of 0°C to 70°C — suitable for indoor equipment, test gear, and telecom line cards where ambient stays within a conditioned environment. ## What the 15 ns access time means for your bus design 15 ns access time means the data appears on the output bus within 15 ns of the address being valid — the memory controller must hold the address stable for that window plus any hold time after chip enable or output enable asserts. The 15 ns write cycle time (word or page) indicates the minimum pulse width for a write operation — shorter pulses risk incomplete data capture. Both ports run independently at this speed, so the arbitration logic (if any) is external.","metaTitle":"Infineon CY7C037V-15AXC 576Kbit Dual-Port SRAM, 15ns","metaDescription":"CY7C037V-15AXC 576Kbit (32K x 18) dual-port asynchronous SRAM, 15 ns access, 3V–3.6V, 100-TQFP. Obsolete — sourced per RFQ through independent distribution.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Obsolete","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"-","Package":"Bag","Technology":"SRAM - Dual Port, Asynchronous","Access Time":"15 ns","Memory Size":"576Kbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"100-LQFP","Product Status":"Obsolete","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"3V ~ 3.6V","Base Product Number":"CY7C037","Memory Organization":"32K x 18","Operating Temperature":"0°C ~ 70°C (TA)","Supplier Device Package":"100-TQFP (14x14)","Write Cycle Time - Word, Page":"15ns"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":null,"stockQuantity":0,"priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/8a0e13f3aa069ed315d5b221233f83a2.pdf","sourceUrl":null},"ai":{"faq":[{"question":"What is the memory organization and interface of CY7C037V-15AXC?","answer":"Organized as 32K x 18 bits (576Kbit total) with a parallel asynchronous interface. Both ports are fully independent — each has its own address, data, and control lines."},{"question":"What package does CY7C037V-15AXC use?","answer":"100-TQFP (14x14 mm), supplier device package 100-TQFP."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C037V-15AXC","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C037V-15AXC when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-21T01:53:05.838Z","lastPublished":"2026-07-21T01:53:05.838Z","indexable":true}}