{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C025-55JXC","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C025-55JXC","canonicalUrl":"https://icboms.com/infineon/CY7C025-55JXC","factsUrl":"https://icboms.com/api/mcp/products/CY7C025-55JXC","rawCanonicalId":null},"summary":{"shortDescription":"Cypress CY7C025-55JXC, 128Kbit (8K x 16) asynchronous dual-port SRAM, 55 ns access time, parallel interface, 4.5 V to 5.5 V supply, 0°C to 70°C, 84-PLCC (29.31 mm x 29.31 mm), surface mount, tray.","salesMarkdown":"## 128Kbit dual-port SRAM with 55 ns access — the shared-memory workhorse The Cypress CY7C025-55JXC is a 128Kbit asynchronous dual-port SRAM organized as 8K words by 16 bits. Its 55 ns access time suits processor-to-processor mailbox or FIFO-style data exchange where both ports need independent read/write access to the same memory array without arbitration dead cycles. At 55 ns the part fits into a 12.5 MHz or slower shared-bus window with no wait states, assuming typical address-to-data setup. If your system clock runs faster, the bus controller must insert wait cycles or you trade throughput for timing margin. The write cycle time matches the access time at 55 ns, so back-to-back writes on the same port are possible at that rate — useful for burst transfers from a DMA controller. ## Package and footprint: 84-PLCC, J-lead Housed in an 84-lead PLCC with J-leads (29.31 mm body square), the part is surface-mountable but requires a PLCC socket or reflow profile tuned for the J-lead geometry. If your application sees ambient below freezing or above 70°C, this part is out of spec. ## Lifecycle reality: obsolete, no direct replacement on record Cypress has marked the CY7C025-55JXC obsolete.","metaTitle":"Cypress CY7C025-55JXC 128Kbit Dual-Port SRAM, 55ns, 84-PLCC","metaDescription":"Cypress CY7C025-55JXC 128Kbit (8K x 16) asynchronous dual-port SRAM, 55ns access time, 4.5V-5.5V, 0°C to 70°C, 84-PLCC.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Obsolete","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"-","Package":"Tray","Technology":"SRAM - Dual Port, Asynchronous","Access Time":"55 ns","Memory Size":"128Kbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"84-LCC (J-Lead)","Product Status":"Obsolete","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"4.5V ~ 5.5V","Base Product Number":"CY7C025","Memory Organization":"8K x 16","Operating Temperature":"0°C~70°C(TA)","Supplier Device Package":"84-PLCC (29.31x29.31)","Write Cycle Time - Word, Page":"55ns"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":null,"stockQuantity":0,"priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/acb212b00bae884886f16db8e44aa706.pdf","sourceUrl":null},"ai":{"faq":[{"question":"Is CY7C025-55JXC obsolete and what is the direct replacement?","answer":"Yes, the CY7C025-55JXC is obsolete per Cypress's product status. Any substitute would need to match the 128Kbit dual-port SRAM function, 55 ns access, 5 V supply, and 84-PLCC package — a non-trivial cross-reference that should be validated against the original PCB footprint and timing."},{"question":"What is the memory size and organization of CY7C025-55JXC?","answer":"The CY7C025-55JXC is a 128Kbit SRAM organized as 8K words by 16 bits, accessed via a parallel interface."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C025-55JXC","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C025-55JXC when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-17T19:50:00.618Z","lastPublished":"2026-07-17T19:50:00.618Z","indexable":true}}