{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C025-25JXC","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C025-25JXC","canonicalUrl":"https://icboms.com/infineon/CY7C025-25JXC","factsUrl":"https://icboms.com/api/mcp/products/CY7C025-25JXC","rawCanonicalId":null},"summary":{"shortDescription":"Cypress CY7C025-25JXC, 128Kbit (8K x 16) asynchronous dual-port SRAM, 25 ns access time, 4.5V–5.5V supply, 84-PLCC (J-Lead), 0°C to 70°C.","salesMarkdown":"For sustainment of existing designs, the only channel is the independent distribution market — surplus, new-old-stock, or qualified broker inventory. Any replacement would require a form-fit-function evaluation of a different dual-port SRAM family or a redesign around a FIFO or shared-RAM architecture. In a dual-port configuration where two independent buses (e.g., a DSP and an FPGA) share this memory, 25 ns sets the minimum bus cycle time for each port. If your system clock runs at 40 MHz (25 ns period), this part gives zero wait-state reads on both ports simultaneously — but only if the address hold and data setup margins are clean. At 50 MHz (20 ns period), you will need at least one wait state on one port. ## 128Kbit organized as 8K x 16 — sizing the buffer The 128Kbit memory is organized as 8K words of 16 bits each. For a dual-port SRAM used as a shared mailbox between two processors, 8K words is enough for moderate-sized command queues or status tables. ## 84-PLCC J-Lead — legacy footprint, rework considerations The 84-LCC (J-Lead) package body measures 29.31 mm square. J-Lead packages are less common in modern production lines than QFP or BGA; rework requires a hot-air nozzle sized for the PLCC body. ## Supply and temperature — fit check This is important: if your system runs on 3.3 V or lower, this part needs a separate 5 V rail or a level translator on the address/data buses. The part is surface-mount only, in the 84-PLCC package.","metaTitle":"Cypress CY7C025-25JXC 128Kbit Dual-Port SRAM, 25 ns, 84-PLCC","metaDescription":"Cypress CY7C025-25JXC 128Kbit (8K x 16) asynchronous dual-port SRAM, 25 ns access time, 4.5V–5.5V, 84-PLCC.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Obsolete","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"-","Package":"Tube","Technology":"SRAM - Dual Port, Asynchronous","Access Time":"25 ns","Memory Size":"128Kbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"84-LCC (J-Lead)","Product Status":"Obsolete","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"4.5V ~ 5.5V","Base Product Number":"CY7C025","Memory Organization":"8K x 16","Operating Temperature":"0°C ~ 70°C (TA)","Supplier Device Package":"84-PLCC (29.31x29.31)","Write Cycle Time - Word, Page":"25ns"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":null,"stockQuantity":0,"priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/24372a262b0fdee4cfbd53405e7a28a5.pdf","sourceUrl":null},"ai":{"faq":[{"question":"What is the replacement for CY7C025-25JXC?","answer":"There is no official pin-compatible replacement from Cypress/Infineon. A form-fit-function replacement would require evaluating a different dual-port SRAM family (e.g., the CY7C026 series in a similar PLCC package, but with different density) or redesigning around a FIFO or shared-RAM architecture. The independent channel is the practical source for this exact part."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C025-25JXC","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C025-25JXC when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-17T19:50:00.618Z","lastPublished":"2026-07-17T19:50:00.618Z","indexable":true}}