{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY7C025-15AXCT","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY7C025-15AXCT","canonicalUrl":"https://icboms.com/infineon/CY7C025-15AXCT","factsUrl":"https://icboms.com/api/mcp/products/CY7C025-15AXCT","rawCanonicalId":null},"summary":{"shortDescription":"Cypress CY7C025-15AXCT, 128Kbit (8K x 16) Dual-Port Asynchronous SRAM, 15 ns access time, Parallel interface, 4.5V to 5.5V supply, 0°C to 70°C, 100-TQFP (14x14), Tape & Reel.","salesMarkdown":"## What this dual-port SRAM does The Cypress CY7C025-15AXCT is a 128Kbit dual-port asynchronous SRAM organized as 8K words by 16 bits. Its two independent ports let two bus masters — two microcontrollers, a DSP and an FPGA, or a CPU and a DMA controller — read and write the same memory array without arbitration logic. Each port has its own chip enable, output enable, and write enable pins, plus separate address and data buses. For a system running a 50 MHz bus (20 ns cycle), this part leaves 5 ns of margin for address setup, hold, and propagation delay through buffers or level shifters. At 66 MHz (15 ns cycle), the access time exactly matches the bus period, so zero-wait-state operation is possible only if the board layout keeps trace lengths short and the address-to-data path clean. ## 5V-only supply — plan for level translation If your host processor runs at 3.3V or 1.8V, every address, data, and control pin on both ports needs bidirectional level translation. The 15 ns access time budget shrinks by the propagation delay of the translator, so choose a fast translator (sub-5 ns) to keep the bus margin intact. Cypress lists the CY7C025-15AXCT as obsolete. No last-time-buy window remains open from the manufacturer. There is no pin-compatible direct replacement from Cypress (now Infineon) in the same dual-port family; the closest functional alternatives use different packages or supply voltages and require a board spin. If you need a drop-in substitute, verify the exact footprint and timing against the original design before committing.","metaTitle":"CY7C025-15AXCT Cypress 128Kbit Dual-Port SRAM, 15 ns","metaDescription":"Cypress CY7C025-15AXCT 128Kbit (8K x 16) dual-port asynchronous SRAM, 15 ns access time, 100-TQFP.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Obsolete","categoryPath":["Memory (DRAM / SRAM / Flash / EEPROM)"],"specifications":{"Mfr":"Infineon Technologies","Series":"-","Package":"Tape & Reel (TR)","Technology":"SRAM - Dual Port, Asynchronous","Access Time":"15 ns","Memory Size":"128Kbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"100-LQFP","Product Status":"Obsolete","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"4.5V ~ 5.5V","Base Product Number":"CY7C025","Memory Organization":"8K x 16","Operating Temperature":"0°C ~ 70°C (TA)","Supplier Device Package":"100-TQFP (14x14)","Write Cycle Time - Word, Page":"15ns"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":null,"stockQuantity":0,"priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/24372a262b0fdee4cfbd53405e7a28a5.pdf","sourceUrl":null},"ai":{"faq":[{"question":"Is CY7C025-15AXCT obsolete?","answer":"Yes, Cypress has marked the CY7C025-15AXCT as obsolete. No further production is planned. The part can be sourced through independent distribution channels; submit an RFQ for current availability and pricing."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY7C025-15AXCT","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY7C025-15AXCT when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-17T19:50:00.618Z","lastPublished":"2026-07-17T19:50:00.618Z","indexable":true}}