{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY62128VLL-70ZAIT","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY62128VLL-70ZAIT","canonicalUrl":"https://icboms.com/infineon/CY62128VLL-70ZAIT","factsUrl":"https://icboms.com/api/mcp/products/CY62128VLL-70ZAIT","rawCanonicalId":null},"summary":{"shortDescription":"Infineon Technologies MoBL SRAM family, asynchronous SRAM, CY62128VLL-70ZAIT, 1 Mbit (128K x 8), 70 ns access time, 2.7-3.6 V, -40 to 85°C, 32-TSOP II, Bulk.","salesMarkdown":"## Active 1 Mbit async SRAM in 32-TSOP — what the 70 ns access means for bus timing The CY62128VLL-70ZAIT is an Infineon Technologies asynchronous SRAM organized as 128K × 8 bits (1 Mbit total), in a surface-mount 32-TSOP II package. It is part of the MoBL (More Battery Life) family, designed for low-power standby in battery-backed or portable applications. The 70 ns access time means the part can present valid data on the bus within 70 ns of the address being stable — this sets the minimum read-cycle period for the memory controller. For a typical 8-bit microcontroller or CPLD bus running at 10-12 MHz, this is comfortable; at 20 MHz the bus cycle drops to 50 ns and the part cannot keep up without wait states. ## Supply rail and temperature grade — 2.7-3.6 V single-rail, -40 to 85°C The 70 ns write cycle time matches the read access, so the bus timing is symmetric — no need to stretch write cycles beyond the read period. The 32-TSOP II body width is 11.80 mm — a standard footprint shared with many 8-bit SRAM and flash parts, so the PCB layout is not exotic. ## Active lifecycle — no NRND, no EOL notice on record There is no last-time-buy window, no NRND flag, and no official successor part number published.","metaTitle":"Infineon CY62128VLL-70ZAIT SRAM, 1 Mbit, 70 ns, 32-TSOP","metaDescription":"Active-production Infineon CY62128VLL-70ZAIT asynchronous SRAM, 128K x 8, 70 ns access, 2.7-3.6 V, -40 to 85°C, 32-TSOP. Sourced to order.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":"Not applicable","productStatus":"Active","categoryPath":["Discrete Semiconductors"],"specifications":{"Package":"Bulk","Technology":"SRAM - Asynchronous","Access Time":"70 ns","Memory Size":"1Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"32-TFSOP (0.465\\\", 11.80mm Width)","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"2.7V ~ 3.6V","Memory Organization":"128K x 8","Operating Temperature":"-40°C ~ 85°C (TA)","Supplier Device Package":"32-TSOP","Write Cycle Time - Word, Page":"70ns"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$1.11","stockQuantity":0,"priceTiers":[{"qty":270,"price":"$1.11000","currency":"USD"}]},"links":{"datasheetUrl":"https://cdn.icboms.com/8f0064260806244ad52fefedc91ccaa7.pdf","sourceUrl":null},"ai":{"faq":[{"question":"What is the memory organization and interface of CY62128VLL-70ZAIT?","answer":"It is organized as 128K words × 8 bits (1 Mbit total) with a parallel interface. The byte-wide data bus connects directly to an 8-bit microcontroller or CPLD without multiplexing."},{"question":"What package does CY62128VLL-70ZAIT come in?","answer":"It is supplied in a 32-TSOP II package (32-TFSOP, 0.465\" body width, 11.80 mm), surface-mount, with a Bulk shipping format."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY62128VLL-70ZAIT","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY62128VLL-70ZAIT when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-22T19:45:10.375Z","lastPublished":"2026-07-22T19:45:10.375Z","indexable":true}}