{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY62128DV30LL-55SXIT","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY62128DV30LL-55SXIT","canonicalUrl":"https://icboms.com/infineon/CY62128DV30LL-55SXIT","factsUrl":"https://icboms.com/api/mcp/products/CY62128DV30LL-55SXIT","rawCanonicalId":null},"summary":{"shortDescription":"Cypress MoBL® asynchronous SRAM, CY62128DV30LL-55SXIT, 1Mbit (128K x 8), 55 ns access, 2.2V-3.6V supply, industrial temp, 32-SOIC wide-body package, Bulk.","salesMarkdown":"## 55 ns access — what it means for bus timing The CY62128DV30LL-55SXIT: For a 16 MHz MCU with a 62.5 ns cycle, this SRAM fits a single-wait-state read; at 20 MHz (50 ns cycle) the access time forces a wait state or a slower clock on the memory bus. The write cycle time matches the read at 55 ns (word and page mode), so the bus timing budget is symmetric — no need to stretch the write pulse separately. ## Supply range and standby current profile The MoBL (More Battery Life) series is optimized for low standby current — relevant when this SRAM sits on a battery-backed bus or in a low-power data logger that keeps the memory powered during sleep. Supplied in Bulk tube — not tape-and-reel — so it suits prototype runs and low-volume production where a pick-and-place feeder changeover is not justified.","metaTitle":"CY62128DV30LL-55SXIT SRAM, 1Mbit, 55ns, 32-SOIC","metaDescription":"Active Cypress MoBL 1Mbit async SRAM, 55ns access, 2.2-3.6V, -40 to 85°C. 32-SOIC. Sourced to order against RFQ.","metaKeywords":null},"attributes":{"series":"MoBL®","packageCase":null,"mountingType":null,"rohsStatus":"Not applicable","productStatus":"Active","categoryPath":["Interface & Transceivers"],"specifications":{"Series":"MoBL®","Package":"Bulk","Technology":"SRAM - Asynchronous","Access Time":"55 ns","Memory Size":"1Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"32-SOIC (0.445\\\", 11.30mm Width)","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"2.2V ~ 3.6V","Memory Organization":"128K x 8","Operating Temperature":"-40°C ~ 85°C (TA)","Supplier Device Package":"32-SOIC","Write Cycle Time - Word, Page":"55ns"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$2.01","stockQuantity":26,"priceTiers":[{"qty":150,"price":"$2.01000","currency":"USD"}]},"links":{"datasheetUrl":null,"sourceUrl":null},"ai":{"faq":[{"question":"How do I get current pricing and availability for CY62128DV30LL-55SXIT?","answer":"Submit an RFQ through this listing."},{"question":"What is the memory organization and interface of this SRAM?","answer":"Organized as 128K words by 8 bits (128K x 8) with a parallel asynchronous interface. The 8-bit data bus connects directly to an 8-bit MCU or a byte-wide peripheral bus without external muxing."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY62128DV30LL-55SXIT","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY62128DV30LL-55SXIT when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-22T19:45:10.375Z","lastPublished":"2026-07-22T19:45:10.375Z","indexable":true}}