{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY62128DV30L-70SI","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY62128DV30L-70SI","canonicalUrl":"https://icboms.com/infineon/CY62128DV30L-70SI","factsUrl":"https://icboms.com/api/mcp/products/CY62128DV30L-70SI","rawCanonicalId":null},"summary":{"shortDescription":"Infineon MoBL® CY62128DV30L-70SI, 1 Mbit asynchronous SRAM, 128K x 8 organization, 70 ns access time, 2.2 V to 3.6 V supply, parallel interface, -40°C to 85°C, 32-SOIC.","salesMarkdown":"## MoBL 1 Mbit async SRAM — 70 ns access, byte-wide bus, industrial temp The Infineon CY62128DV30L-70SI is a 1 Mbit asynchronous SRAM from the MoBL® series, organized as 128K x 8 bits with a 70 ns access time. It operates from a 2.2 V to 3.6 V supply and communicates over a parallel interface. The part is rated for -40°C to 85°C, making it suitable for industrial control, outdoor telecom, and factory automation where the memory bus needs deterministic read-write timing without refresh overhead. ## 70 ns access — what it means for bus timing The 70 ns access time defines the window from address valid to data valid on a read cycle. The 70 ns write cycle time is symmetrical, so the bus timing budget is the same for both read and write operations. ## 128K x 8 organization — byte-wide fit The 128K x 8 organization presents an 8-bit data bus. This directly matches 8-bit MCUs and DSPs without external byte-lane steering logic. ## Industrial temperature range and package The -40°C to 85°C operating range qualifies the part for environments where the enclosure sees outdoor temperature swings, such as base stations, solar inverters, and motor drives. The 32-SOIC (0.445\" body width) is a surface-mount footprint common in industrial PCBs; it is not a fine-pitch BGA, so hand rework and inspection are straightforward. ## RoHS non-compliant — legacy solder finish This part is marked RoHS non-compliant, meaning the terminations use a tin-lead (SnPb) finish. It cannot be used in a lead-free reflow process without a RoHS exemption or waiver. For new designs requiring RoHS compliance, a lead-free variant from the MoBL family should be selected. For legacy production lines that still run SnPb solder, this part is a direct fit. ## Active lifecycle — no LTB pressure The CY62128DV30L-70SI carries an Active lifecycle status from Infineon (Cypress). There is no last-time-buy notice, no NRND flag, and no announced end-of-life.","metaTitle":"CY62128DV30L-70SI Infineon MoBL SRAM, 1 Mbit, 70 ns","metaDescription":"Infineon CY62128DV30L-70SI MoBL asynchronous SRAM, 1 Mbit (128K x 8), 70 ns access, -40 to 85°C, 32-SOIC. Active lifecycle, RoHS non-compliant.","metaKeywords":null},"attributes":{"series":"MoBL®","packageCase":null,"mountingType":null,"rohsStatus":"RoHS non-compliant","productStatus":"Active","categoryPath":["Analog & Data Acquisition"],"specifications":{"Series":"MoBL®","Package":"Bulk","Technology":"SRAM - Asynchronous","Access Time":"70 ns","Memory Size":"1Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"32-SOIC (0.445\\\", 11.30mm Width)","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"2.2V ~ 3.6V","Memory Organization":"128K x 8","Operating Temperature":"-40°C ~ 85°C (TA)","Supplier Device Package":"32-SOIC","Write Cycle Time - Word, Page":"70ns"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$1.87","stockQuantity":0,"priceTiers":[{"qty":161,"price":"$1.87000","currency":"USD"}]},"links":{"datasheetUrl":"https://rocelec.widen.net/view/pdf/zhxocyj1d7/CYPRS05895-1.pdf?t.download=true&u=5oefqw","sourceUrl":null},"ai":{"faq":[{"question":"Is CY62128DV30L-70SI RoHS compliant?","answer":"No, the CY62128DV30L-70SI is listed as RoHS non-compliant. The terminations use a tin-lead (SnPb) finish, so it is not suitable for lead-free reflow processes without a RoHS exemption."},{"question":"What is the access time of CY62128DV30L-70SI?","answer":"The access time is 70 ns for both read and write cycles. This is the time from address valid to data valid on a read, and the minimum write pulse width on a write."},{"question":"What is the closest functional second-source for CY62128DV30L-70SI?","answer":"The CY7C1018DV33-10VXI is a 1 Mbit (128K x 8) asynchronous SRAM in the same 32-SOIC footprint with a 10 ns access time and 3.0 V supply. It is a faster alternative, but verify pin-compatibility and the supply voltage tolerance before substituting."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY62128DV30L-70SI","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY62128DV30L-70SI when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-17T19:50:00.618Z","lastPublished":"2026-07-17T19:50:00.618Z","indexable":true}}