{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY2V995AI","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY2V995AI","canonicalUrl":"https://icboms.com/infineon/CY2V995AI","factsUrl":"https://icboms.com/api/mcp/products/CY2V995AI","rawCanonicalId":null},"summary":{"shortDescription":"Cypress CY2V995AI Zero Delay Buffer, PLL based clock driver, 200 MHz max, LVCMOS/LVTTL input, LVTTL output, 2:8 fanout, 44-TQFP, -40 to 85°C, dual supply 2.375V–2.625V / 2.97V–3.63V.","salesMarkdown":"## PLL-based zero delay buffer for clock distribution The Cypress CY2V995AI is a PLL-based zero delay buffer designed to regenerate a clock signal with minimal phase shift between input and output. It accepts LVCMOS or LVTTL inputs and delivers LVTTL outputs across eight fanout paths from two input sources (2:8 ratio), making it a fit for distributing a clean, low-skew clock to multiple loads in a system. Rated for a maximum operating frequency of 200 MHz, this part suits clock trees in networking gear, base stations, test equipment, and industrial controllers where timing margin matters. The industrial temperature range of -40°C to 85°C covers outdoor telecom cabinets and factory-floor automation without requiring a commercial-grade workaround. ## Supply voltage flexibility and package The CY2V995AI operates from two distinct supply ranges: 2.375V to 2.625V and 2.97V to 3.63V. This dual-range support lets the same part work in a 2.5V or 3.3V logic environment without a separate voltage translator on the clock line — a BOM simplification when mixing FPGA banks and ASIC I/O. Housed in a 44-TQFP (10x10 mm) surface-mount package. ## Lifecycle and sourcing posture For a BOM line that needs a zero delay buffer, this part carries no near-term obsolescence risk. Note that the RoHS compliance status is marked non-compliant, so verify your assembly's exemption or waiver requirements for a lead-free reflow process.","metaTitle":"CY2V995AI Zero Delay Buffer, 200 MHz, 44-TQFP","metaDescription":"Cypress CY2V995AI zero delay buffer, 200 MHz max, LVCMOS/LVTTL input, LVTTL output, 2:8 fanout, 44-TQFP, -40 to 85°C. Active lifecycle.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":"RoHS non-compliant","productStatus":"Active","categoryPath":["Clock & Timing ICs"],"specifications":{"Type":"Zero Delay Buffer","Input":"LVCMOS, LVTTL","Output":"LVTTL","Package":"Bulk","Mounting Type":"Surface Mount","Package / Case":"44-TQFP","Frequency - Max":"200 MHz","lifecycle_stage":"eol_hot","Voltage - Supply":"2.375V ~ 2.625V, 2.97V ~ 3.63V","Number of Circuits":"1","Ratio - Input:Output":"2:8","Operating Temperature":"-40°C ~ 85°C (TA)","Supplier Device Package":"44-TQFP (10x10)","Differential - Input:Output":"No/No"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$4.38","stockQuantity":0,"priceTiers":[{"qty":69,"price":"$4.38000","currency":"USD"}]},"links":{"datasheetUrl":"https://cdn.icboms.com/dc3a5466cbb8e717b4a6025326e96676.pdf","sourceUrl":null},"ai":{"faq":[{"question":"Is CY2V995AI a zero delay buffer?","answer":"Yes, the CY2V995AI is a PLL-based zero delay buffer. It regenerates the input clock with minimal phase offset, which is the defining function of this device class."},{"question":"Does CY2V995AI support LVCMOS input?","answer":"Yes, the CY2V995AI accepts both LVCMOS and LVTTL input signals. Outputs are LVTTL."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY2V995AI","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY2V995AI when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-17T19:50:00.618Z","lastPublished":"2026-07-17T19:50:00.618Z","indexable":true}}