{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY28347ZCT","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY28347ZCT","canonicalUrl":"https://icboms.com/infineon/CY28347ZCT","factsUrl":"https://icboms.com/api/mcp/products/CY28347ZCT","rawCanonicalId":null},"summary":{"shortDescription":"Cypress CY28347ZCT, processor-specific clock generator, PLL Yes, Input Clock, Output Clock, DDR main purpose, 200 MHz max, 2.375V–2.625V / 3.135V–3.465V supply, 1:18 input:output, differential I/O, 0°C–70°C, 56-TFSOP (0.240\", 6.10mm Width), Surface Mount.","salesMarkdown":"## DDR clock generator with PLL and 18 outputs The Cypress CY28347ZCT is a processor-specific clock generator built around a PLL, designed to produce clean, low-jitter clock signals for DDR memory systems. It accepts a single clock input and fans it out to 18 clock outputs, with a maximum output frequency of 200 MHz. The part integrates two PLL circuits, allowing it to generate two independent clock domains from one reference — useful for separating the memory controller clock from the I/O or chipset clock on a motherboard or server blade. The input and output signals are differential (Yes/Yes), so the part works with LVDS or LVPECL-level clocks. That differential signalling keeps jitter low across the board, which is what DDR timing margins depend on. The 1:18 input-to-output ratio means one reference clock feeds up to 18 loads — DIMM slots, PCH, or other clock sinks — without needing external fanout buffers. ## Supply rails and temperature grade The CY28347ZCT operates on two supply ranges: 2.375 V to 2.625 V for the PLL core, and 3.135 V to 3.465 V for the output buffers. The operating temperature range is 0°C to 70°C. ## Lifecycle and sourcing The product status is Active. No direct pin-compatible second source is confirmed in the record.","metaTitle":"Cypress CY28347ZCT DDR Clock Generator, PLL, 200 MHz","metaDescription":"Cypress CY28347ZCT processor-specific clock generator for DDR. PLL with 200 MHz max, 1:18 fanout, dual supply.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":"RoHS non-compliant","productStatus":"Active","categoryPath":["Discrete Semiconductors"],"specifications":{"PLL":"Yes","Input":"Clock","Output":"Clock","Package":"Bulk","Main Purpose":"DDR","Mounting Type":"Surface Mount","Package / Case":"56-TFSOP (0.240\\\", 6.10mm Width)","Frequency - Max":"200MHz","lifecycle_stage":"eol_hot","Voltage - Supply":"2.375V ~ 2.625V, 3.135V ~ 3.465V","Number of Circuits":"2","Ratio - Input:Output":"1:18","Operating Temperature":"0°C ~ 70°C (TA)","Supplier Device Package":"56-TSSOP II","Differential - Input:Output":"Yes/Yes"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$3.18","stockQuantity":0,"priceTiers":[{"qty":95,"price":"$3.18000","currency":"USD"}]},"links":{"datasheetUrl":"https://cdn.icboms.com/e52d3ff8cde6be94a996c11a58e5f64f.pdf","sourceUrl":null},"ai":{"faq":[{"question":"What voltage does CY28347ZCT require?","answer":"It requires two supply rails: a 2.375 V to 2.625 V supply for the PLL core, and a 3.135 V to 3.465 V supply for the output buffers."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY28347ZCT","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY28347ZCT when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-17T19:50:00.618Z","lastPublished":"2026-07-17T19:50:00.618Z","indexable":true}}