{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY26580OI-1","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY26580OI-1","canonicalUrl":"https://icboms.com/infineon/CY26580OI-1","factsUrl":"https://icboms.com/api/mcp/products/CY26580OI-1","rawCanonicalId":null},"summary":{"shortDescription":"Cypress Semiconductor PacketClock™ clock generator, fanout distribution, multiplexer, CY26580OI-1, 133.33 MHz max, PLL with bypass, 1:2 I/O, 3.14-3.47 V, -40 to 85°C, 20-SSOP, Bulk.","salesMarkdown":"## 133.33 MHz PLL clock source with bypass — BOM-fit note The CY26580OI-1 is a PacketClock™ clock generator that also integrates fanout distribution and a multiplexer in a single 20-SSOP package. Its maximum output frequency of 133.33 MHz sets the clock ceiling for the target interface — typically a SONET/SDH or Ethernet framer that needs a clean reference at that rate. The on-chip PLL includes a bypass mode (: PLL Yes with Bypass), meaning the reference clock can pass through unmodified when the system needs a jitter-free path or during board-level debug. Input and output are both single-ended CMOS, not differential — the fanout stays within a single board, not a backplane. The industrial temperature range (-40°C to 85°C,) suits outdoor telecom cabinets or factory-floor controllers where ambient heat cycles are the norm. ## Package and supply integration The supplier device package is listed as 20-QSOP — the QSOP variant shares the same footprint but has a thinner body; both are surface-mount and reflow-compatible. Single PLL circuit with a 1:2 input-to-output ratio — one reference clock drives two output trees. The divider/multiplier block is present (Yes/No,), so the PLL can multiply the reference up to the 133.33 MHz ceiling or divide it down for lower-speed domains.","metaTitle":"CY26580OI-1 Clock Generator, 133.33 MHz, 20-SSOP","metaDescription":"CY26580OI-1 PacketClock™ clock generator, fanout distribution, multiplexer. 133.33 MHz max, PLL with bypass, 3.14-3.47 V, -40 to 85°C. Active lifecycle.","metaKeywords":null},"attributes":{"series":"PacketClock™","packageCase":null,"mountingType":null,"rohsStatus":"Not applicable","productStatus":"Active","categoryPath":["Clock & Timing ICs"],"specifications":{"PLL":"Yes with Bypass","Type":"Clock Generator, Fanout Distribution, Multiplexer","Input":"CMOS","Output":"Clock","Series":"PacketClock™","Package":"Bulk","Mounting Type":"Surface Mount","Package / Case":"20-SSOP (0.154\\\", 3.90mm Width)","Frequency - Max":"133.33MHz","lifecycle_stage":"eol_hot","Voltage - Supply":"3.14V ~ 3.47V","Divider/Multiplier":"Yes/No","Number of Circuits":"1","Ratio - Input:Output":"1:2","Operating Temperature":"-40°C ~ 85°C (TA)","Supplier Device Package":"20-QSOP","Differential - Input:Output":"No/No"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$1.48","stockQuantity":0,"priceTiers":[{"qty":204,"price":"$1.48000","currency":"USD"}]},"links":{"datasheetUrl":"https://cdn.icboms.com/ea3418420ff3c8651aaf955b0250e37d.pdf","sourceUrl":null},"ai":{"faq":[{"question":"What is the PLL configuration on the CY26580OI-1?","answer":"The PLL is listed as Yes with Bypass. This means the internal phase-locked loop can be engaged for frequency synthesis or bypassed entirely, letting the reference clock pass through unmodified. Input and output are both single-ended CMOS; there is no differential I/O."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY26580OI-1","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY26580OI-1 when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}