{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CY23FP12OC","brand":"Infineon Technologies","brandSlug":"infineon","productSlug":"CY23FP12OC","canonicalUrl":"https://icboms.com/infineon/CY23FP12OC","factsUrl":"https://icboms.com/api/mcp/products/CY23FP12OC","rawCanonicalId":null},"summary":{"shortDescription":"Cypress CY23FP12OC, PLL-based Zero Delay Buffer, Fanout Buffer (Distribution), 200 MHz max, 2:12 LVCMOS I/O, 28-SSOP, 0°C to 70°C, RoHS non-compliant.","salesMarkdown":"## PLL-based clock distribution in a 28-pin SSOP The CY23FP12OC is a PLL-based zero delay buffer from Cypress, designed to regenerate a clean clock output with deterministic phase alignment relative to the input. It accepts a single LVCMOS or LVTTL reference and distributes it across 12 LVCMOS outputs, all phase-locked to the incoming edge. The internal PLL multiplies the reference to generate the output frequency, but the divider path is not engaged — the ratio is set by the PLL feedback path, not an external divider. Maximum output frequency is 200 MHz, which covers most common system clocks for Ethernet PHYs, FPGAs, and SoC reference inputs. Supply voltage covers 2.375 V to 2.625 V and 3.135 V to 3.465 V. Packaged in a 28-SSOP with 0.209-inch body width and 5.30 mm height, surface-mount only. The 28-pin count is driven by the 12 outputs plus power, ground, and feedback paths — not a dense package, but the pin pitch is fine enough that hand rework requires care. Commercial temperature range (0°C to 70°C) limits this part to indoor, controlled environments; no industrial or automotive variants are listed in this order code. ## What the 2:12 ratio and 200 MHz ceiling mean for your clock tree The 2:12 input-to-output ratio means two input pins feed a single PLL that drives 12 identical LVCMOS outputs. The 200 MHz maximum frequency is the upper bound for the output. Differential inputs and outputs are not supported — all I/O are single-ended LVCMOS. The zero-delay characteristic means the output edges align to the input edge within the PLL's lock range, which is useful for source-synchronous interfaces where the clock and data must maintain a fixed phase relationship across the board. ## Active lifecycle, but watch the RoHS status That means no last-time-buy pressure and no forced redesign for obsolescence. However, the RoHS compliance status is listed as non-compliant. This part contains lead in the solder finish or internal construction, which excludes it from builds destined for RoHS-enforced markets (EU, California, etc.) unless a specific exemption applies. If your BOM requires full RoHS compliance, you will need a different order code or a lead-free equivalent, though no direct RoHS-compliant alternate is listed in this record. ## Sourcing posture: quoted to order This part is sourced through independent distribution channels and quoted to order against an RFQ. For a BOM line that needs this exact Cypress order code, the procurement path is a request for quote with quantity and target delivery window. Given the Active status, lead times are generally stable, but the RoHS restriction may narrow the pool of available inventory, so early engagement is advisable for production volumes.","metaTitle":"CY23FP12OC PLL Clock Driver, 200 MHz, 28-SSOP","metaDescription":"CY23FP12OC PLL-based zero delay fanout buffer, 2:12 LVCMOS outputs, 200 MHz max, 28-SSOP. Active lifecycle, RoHS non-compliant.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":"RoHS non-compliant","productStatus":"Active","categoryPath":["Clock & Timing ICs"],"specifications":{"PLL":"Yes","Type":"Fanout Buffer (Distribution), Zero Delay Buffer","Input":"LVCMOS, LVTTL","Output":"LVCMOS","Package":"Bulk","Mounting Type":"Surface Mount","Package / Case":"28-SSOP (0.209\\\", 5.30mm Width)","Frequency - Max":"200MHz","lifecycle_stage":"eol_hot","Voltage - Supply":"2.375V ~ 2.625V, 3.135V ~ 3.465V","Divider/Multiplier":"Yes/No","Number of Circuits":"1","Ratio - Input:Output":"2:12","Operating Temperature":"0°C ~ 70°C (TA)","Supplier Device Package":"28-SSOP","Differential - Input:Output":"No/No"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$3.01","stockQuantity":0,"priceTiers":[{"qty":100,"price":"$3.01000","currency":"USD"}]},"links":{"datasheetUrl":"https://cdn.icboms.com/b5e0d8ceefaeff39587c6ee85b941347.pdf","sourceUrl":null},"ai":{"faq":[{"question":"Is CY23FP12OC compatible with 2.5V or 3.3V input?","answer":"It accepts both. The supply voltage range covers 2.375 V to 2.625 V for 2.5 V rails and 3.135 V to 3.465 V for 3.3 V rails. The same part works on either supply without a regulator change."},{"question":"How many outputs does CY23FP12OC have?","answer":"The CY23FP12OC provides 12 LVCMOS outputs from a single PLL, with a 2:12 input-to-output ratio. Two input pins (reference and feedback) feed the PLL, and all 12 outputs are phase-aligned to the input edge."},{"question":"What is the difference between CY23FP12OC and CY23FP12OCT?","answer":"The suffix 'T' typically indicates Tape & Reel packaging for automated pick-and-place assembly, while the 'OC' variant ships in Bulk (tubes or trays). Electrically and functionally they are identical — same PLL, same 2:12 ratio, same 200 MHz ceiling. The choice is driven by your assembly line's feeder requirements."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/infineon/CY23FP12OC","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/infineon/CY23FP12OC when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-17T19:50:00.618Z","lastPublished":"2026-07-17T19:50:00.618Z","indexable":true}}