{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CDCEL913PWR","brand":"Texas Instruments","brandSlug":"texas-instruments","productSlug":"CDCEL913PWR","canonicalUrl":"https://icboms.com/texas-instruments/CDCEL913PWR","factsUrl":"https://icboms.com/api/mcp/products/CDCEL913PWR","rawCanonicalId":null},"summary":{"shortDescription":"Texas Instruments CDCEL913PWR PLL Clock Synthesizer, 1 PLL with Bypass, 230 MHz max, LVCMOS I/O, 1.7V-1.9V supply, 14-TSSOP, -40°C to 85°C.","salesMarkdown":"## 230 MHz PLL clock synthesizer for 1.8V logic domains The CDCEL913PWR is a single-PLL clock synthesizer from Texas Instruments that takes an LVCMOS or crystal input and delivers three LVCMOS outputs at up to 230 MHz. The PLL includes a bypass mode (Yes with Bypass), which lets the reference clock pass through unmodified — useful for system test, low-jitter paths, or when the PLL must be disabled during a specific power sequence. The 1:3 input-to-output ratio means a single reference fans out to three independent synthesized clocks, each programmable via the VCXO interface. The LVCMOS I/O levels are 1.8V compatible, so no level translation is needed when connecting to a 1.8V FPGA bank or a low-voltage microcontroller. The base product number CDCEL913 covers the family; the PWR suffix denotes the 14-TSSOP package in tape-and-reel or cut-tape format. RoHS3 compliant, with no exemptions that would restrict EU or UKCA market entry.","metaTitle":"Texas Instruments CDCEL913PWR PLL Clock Synthesizer, 230 MHz","metaDescription":"Active PLL clock synthesizer from TI, 230 MHz max, 1.7-1.9V supply, 14-TSSOP. Industrial temp range. Sourced to order against RFQ.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":"ROHS3 Compliant","productStatus":"Active","categoryPath":["Clock & Timing ICs"],"specifications":{"Mfr":"Texas Instruments","PLL":"Yes with Bypass","Type":"PLL Clock Synthesizer","Input":"LVCMOS, Crystal","Output":"LVCMOS","Series":"-","Package":"Tape & Reel (TR); Cut Tape (CT)","Mounting Type":"Surface Mount","Package / Case":"14-TSSOP (0.173\\\", 4.40mm Width)","Product Status":"Active","Frequency - Max":"230MHz","lifecycle_stage":"eol_hot","Voltage - Supply":"1.7V ~ 1.9V","Divider/Multiplier":"Yes/Yes","Number of Circuits":"1","Base Product Number":"CDCEL913","Ratio - Input:Output":"1:3","Operating Temperature":"-40°C~85°C","Supplier Device Package":"14-TSSOP","Differential - Input:Output":"No/No"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$3.9600","priceTiers":[{"qty":1,"price":"$3.96000","currency":"USD"},{"qty":10,"price":"$3.55200","currency":"USD"},{"qty":25,"price":"$3.35800","currency":"USD"},{"qty":100,"price":"$2.91030","currency":"USD"},{"qty":250,"price":"$2.76108","currency":"USD"},{"qty":500,"price":"$2.47752","currency":"USD"},{"qty":1000,"price":"$2.11200","currency":"USD"},{"qty":2000,"price":"$2.11200","currency":"USD"}]},"links":{"datasheetUrl":"https://cdn.icboms.com/fbaf9abc24e11227d5735c6c8d1a5fb8.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/CDCEL913PWR/alternatives.json"},"ai":{"faq":[{"question":"What does the PLL bypass mode do on this part?","answer":"The PLL includes a bypass option (Yes with Bypass) that passes the input reference clock directly to the output without frequency synthesis. This is useful for system bring-up, jitter characterization, or when the PLL must be disabled during a specific power-up sequence."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/texas-instruments/CDCEL913PWR","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/texas-instruments/CDCEL913PWR when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}