{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"CDCE913PWG4","brand":"Texas Instruments","brandSlug":"texas-instruments","productSlug":"CDCE913PWG4","canonicalUrl":"https://icboms.com/texas-instruments/CDCE913PWG4","factsUrl":"https://icboms.com/api/mcp/products/CDCE913PWG4","rawCanonicalId":null},"summary":{"shortDescription":"Texas Instruments CDCE913PWG4 Spread Spectrum Clock Driver, PLL Yes with Bypass, LVCMOS Input/Output, 230 MHz max, 14-TSSOP package, Tube.","salesMarkdown":"## Clock-engineer decisions: PLL bypass and spread-spectrum fit The CDCE913PWG4: The integrated PLL includes a bypass mode, letting you route a clean reference through the chip without engaging the synthesis loop — useful when the downstream device needs a jitter-free clock for a critical interface. As a spread-spectrum clock driver, it modulates the output frequency to reduce peak EMI at the fundamental and harmonics, which can lower the cost of shielding or ferrite beads on a densely routed board. The 1:3 input-to-output ratio means a single LVCMOS or crystal source fans out to three LVCMOS clock lines, each programmable up to 230 MHz via the internal divider chain. ## Supply rails and temperature envelope The dual supply range — 1.7 V to 1.9 V and 2.3 V to 3.6 V — lets the core run at a lower voltage while the I/O section matches the logic level of the receiving device, saving a level translator in mixed-voltage designs.","metaTitle":"TI CDCE913PWG4 Spread Spectrum Clock Driver, 230 MHz","metaDescription":"Texas Instruments CDCE913PWG4 active spread spectrum clock driver with PLL bypass, 230 MHz max, LVCMOS I/O, 1.7-3.6V supply, -40°C to 85°C. Sourced to order.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["Clock & Timing ICs"],"specifications":{"Mfr":"Texas Instruments","PLL":"Yes with Bypass","Type":"Spread Spectrum Clock Driver","Input":"LVCMOS, Crystal","Output":"LVCMOS","Series":"-","Package":"Tube","Mounting Type":"Surface Mount","Package / Case":"14-TSSOP (0.173\\\", 4.40mm Width)","Frequency - Max":"230MHz","lifecycle_stage":"eol_hot","Voltage - Supply":"1.7V ~ 1.9V, 2.3V ~ 3.6V","Divider/Multiplier":"Yes/Yes","Number of Circuits":"1","Base Product Number":"CDCE913","Ratio - Input:Output":"1:3","Operating Temperature":"-40°C~85°C","Supplier Device Package":"14-TSSOP","Differential - Input:Output":"No/No"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$178.8000","priceTiers":null},"links":{"datasheetUrl":"https://cdn.icboms.com/ba0bef55450a20cc63da3205726d4713.pdf","sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/CDCE913PWG4/alternatives.json"},"ai":{"faq":[{"question":"What does the PLL bypass mode do on the CDCE913PWG4?","answer":"The PLL bypass mode lets the input clock pass through the device without frequency synthesis, delivering a clean reference clock to the outputs when the jitter of the locked loop is not desired — for example, when clocking a low-jitter ADC or FPGA transceiver."},{"question":"What is the maximum output frequency of the CDCE913PWG4?","answer":"The device supports a maximum output frequency of 230 MHz, limited by the internal PLL and divider chain, with LVCMOS outputs capable of driving standard 50-ohm terminated traces at that speed."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/texas-instruments/CDCE913PWG4","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/texas-instruments/CDCE913PWG4 when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}