{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"AGLN250V5-CSG81I","brand":"Microchip Technology","brandSlug":"microchip","productSlug":"AGLN250V5-CSG81I","canonicalUrl":"https://icboms.com/microchip/AGLN250V5-CSG81I","factsUrl":"https://icboms.com/api/mcp/products/AGLN250V5-CSG81I","rawCanonicalId":null},"summary":{"shortDescription":"Microchip Technology IGLOO nano FPGA, AGLN250V5-CSG81I, 250000 gates, 6144 logic cells, 60 I/O, 81-WFBGA/CSBGA, 1.425V-1.575V, -40°C to 100°C, Tray.","salesMarkdown":"## 81-CSP (5x5) — footprint and board integration The AGLN250V5-CSG81I is a Microchip IGLOO nano FPGA in an 81-ball CSP (5x5 mm) package. The 0.5 mm ball pitch demands a controlled-impedance PCB with via-in-pad or microvia fan-out for the inner rows — a standard 4-layer board with 0.2 mm trace/space handles it, but the outer two rows break out on the top layer without blind vias. The 60 I/O are distributed across the ball map; the CSP's low 0.9 mm seated height suits compact, vibration-tolerant assemblies in handheld or embedded modules. The single 1.425 V to 1.575 V core supply simplifies the power tree — no separate VCCIO rail for the I/O banks (they share the same 1.5 V nominal). The 1.5 V tolerance means a standard 1.5 V LDO or a 1.8 V rail stepped down through a 0.3 V dropout regulator works, provided the output stays inside the 150 mV window. The 100°C TJ ceiling limits the ambient to about 85°C in still air with the CSP's 40°C/W theta-JA — a small heatsink or forced airflow buys margin for the upper end. ## 250K gates, 6144 cells — logic capacity for glue and control With 250,000 system gates and 6144 logic elements, the AGLN250V5-CSG81I fits medium-density glue logic: address decoding, state machines, I/O expansion, or a small microcontroller wrapper. The 36 Kbit (36864 bits) of embedded SRAM supports a single 18 Kbit dual-port block or two 9 Kbit FIFOs — enough for a 256-byte packet buffer or a coefficient lookup table. The 60 user I/O, each configurable as LVCMOS 1.5/1.8/2.5/3.3 V, connect directly to common peripheral buses (SPI, I2C, UART) without external level shifters, as long as the VCCIO matches the interface voltage.","metaTitle":"Microchip AGLN250V5-CSG81I IGLOO nano FPGA, 81-CSP, 60 I/O","metaDescription":"Microchip AGLN250V5-CSG81I IGLOO nano FPGA: 250K gates, 6144 logic cells, 60 I/O, 1.425V-1.575V supply, -40°C to 100°C. Active, RoHS3. Order.","metaKeywords":null},"attributes":{"series":"IGLOO nano","packageCase":null,"mountingType":null,"rohsStatus":"ROHS3 Compliant","productStatus":"Active","categoryPath":["Discrete Semiconductors"],"specifications":{"Series":"IGLOO nano","Package":"Tray","Mounting Type":"Surface Mount","Number of I/O":"60","Package / Case":"81-WFBGA, CSBGA","Total RAM Bits":"36864","Number of Gates":"250000","lifecycle_stage":"eol_hot","Voltage - Supply":"1.425V ~ 1.575V","Operating Temperature":"-40°C ~ 100°C (TJ)","Supplier Device Package":"81-CSP (5x5)","Number of Logic Elements/Cells":"6144"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$33.11","priceTiers":[{"qty":1,"price":"$33.11000","currency":"USD"},{"qty":25,"price":"$26.24000","currency":"USD"},{"qty":100,"price":"$25.28000","currency":"USD"}]},"links":{"datasheetUrl":null,"sourceUrl":null,"alternativesUrl":"https://icboms.com/api/mcp/products/AGLN250V5-CSG81I/alternatives.json"},"ai":{"faq":[],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/microchip/AGLN250V5-CSG81I","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/microchip/AGLN250V5-CSG81I when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}