{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"9FGV0641AKILF","brand":"Renesas Electronics","brandSlug":"renesas","productSlug":"9FGV0641AKILF","canonicalUrl":"https://icboms.com/renesas/9FGV0641AKILF","factsUrl":"https://icboms.com/api/mcp/products/9FGV0641AKILF","rawCanonicalId":null},"summary":{"shortDescription":"Renesas 9FGV0641AKILF PCI Express (PCIe) clock generator, PLL, 1:7 fanout, 100 MHz max, LVDS/Crystal input, HCSL/LVCMOS output, 40-VFQFPN (5x5) exposed pad, tray.","salesMarkdown":"## PCIe clock fanout with integrated PLL The 9FGV0641AKILF is a PCI Express (PCIe) clock generator IC from Renesas, integrating a PLL to synthesize and distribute reference clocks for PCIe lanes. It accepts either an LVDS differential input or a crystal oscillator, and outputs up to seven copies in HCSL or LVCMOS logic levels. The 1:7 fanout ratio means a single clean clock source can feed seven PCIe endpoints or slots, reducing board-level oscillator count and simplifying the clock tree. Maximum output frequency is 100 MHz, covering PCIe Gen 1 through Gen 3 reference clock requirements. ## Supply and temperature envelope The differential input accepts LVDS or a crystal; the output can be configured for HCSL (the PCIe standard) or LVCMOS for legacy logic. ## Active lifecycle and compliance RoHS3 compliant (2011/65/EU + 2015/863), with no exemptions reported.","metaTitle":"9FGV0641AKILF PCIe clock generator, 100 MHz, 1:7 fanout","metaDescription":"Active PCIe clock generator IC, 100 MHz max, 1:7 fanout, LVDS/crystal input, HCSL/LVCMOS output, -40 to 85°C, 40-VFQFPN. RoHS3. Quoted to order.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":"ROHS3 Compliant","productStatus":"Active","categoryPath":["Discrete Semiconductors"],"specifications":{"PLL":"Yes","Input":"LVDS, Crystal","Output":"HCSL, LVCMOS","Package":"Tray","Main Purpose":"PCI Express (PCIe)","Mounting Type":"Surface Mount","Package / Case":"40-VFQFN Exposed Pad","Frequency - Max":"100MHz","lifecycle_stage":"eol_hot","Voltage - Supply":"1.7V ~ 1.9V","Number of Circuits":"1","Ratio - Input:Output":"1:7","Operating Temperature":"-40°C ~ 85°C","Supplier Device Package":"40-VFQFPN (5x5)","Differential - Input:Output":"No/Yes"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$4.15","stockQuantity":0,"priceTiers":[{"qty":1,"price":"$4.15000","currency":"USD"},{"qty":10,"price":"$3.72600","currency":"USD"},{"qty":25,"price":"$3.52240","currency":"USD"},{"qty":80,"price":"$3.05275","currency":"USD"},{"qty":230,"price":"$2.89617","currency":"USD"},{"qty":490,"price":"$2.59873","currency":"USD"},{"qty":980,"price":"$2.19170","currency":"USD"},{"qty":2450,"price":"$2.08211","currency":"USD"},{"qty":4900,"price":"$2.00384","currency":"USD"}]},"links":{"datasheetUrl":"https://cdn.icboms.com/556aa4cbbc998157454f27db82b6e4d3.pdf","sourceUrl":null},"ai":{"faq":[{"question":"What is the input and output interface of 9FGV0641AKILF?","answer":"The input accepts either an LVDS differential signal or a crystal oscillator. The output can be configured as HCSL (the standard for PCIe reference clocks) or LVCMOS, depending on the application's logic level needs."},{"question":"Does 9FGV0641AKILF include a PLL?","answer":"Yes, the device integrates a PLL for clock synthesis and jitter cleaning, enabling it to generate a low-jitter PCIe reference clock from a crystal or a noisy system clock."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/renesas/9FGV0641AKILF","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/renesas/9FGV0641AKILF when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-22T19:45:10.375Z","lastPublished":"2026-07-22T19:45:10.375Z","indexable":true}}