{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"9DB233AGLFT","brand":"Renesas Electronics","brandSlug":"renesas","productSlug":"9DB233AGLFT","canonicalUrl":"https://icboms.com/renesas/9DB233AGLFT","factsUrl":"https://icboms.com/api/mcp/products/9DB233AGLFT","rawCanonicalId":null},"summary":{"shortDescription":"Renesas 9DB233AGLFT PCI Express zero-delay clock fanout buffer, PLL based, 110 MHz max, 1:2 differential HCSL input:output, 3.135V–3.465V supply, 20-TSSOP, 0°C to 70°C.","salesMarkdown":"## PCIe clock distribution — the 110 MHz PLL buffer for Gen1/2/3 reference trees The Renesas 9DB233AGLFT is a zero-delay clock fanout buffer built around an integrated PLL, purpose-designed for PCI Express (PCIe) reference clock distribution. It accepts one differential clock input and delivers two HCSL (High-Speed Current Steering Logic) outputs — the standard signaling level for PCIe — at frequencies up to 110 MHz, which covers the 100 MHz reference clock used across PCIe Gen1, Gen2, and Gen3. The 3.3 V nominal supply (3.135 V to 3.465 V) matches the PCIe clock generator rail, and the 1:2 fanout ratio suits small clock trees where two downstream devices (e.g., a root complex and a switch, or two endpoints) need a clean, phase-aligned copy of the reference. ## 110 MHz ceiling — sized for the PCIe reference, not general-purpose clocking The 110 MHz maximum frequency is the single most important fit criterion. PCIe reference clocks run at 100 MHz; this part has 10 MHz of headroom above that, which covers the nominal frequency plus spread-spectrum modulation and any tolerance. It will not work as a 125 MHz Ethernet reference or a 156.25 MHz SerDes clock — those need a higher-speed PLL. The 1:2 ratio means exactly two output copies; if your PCIe tree needs three or more fanouts, you either cascade another buffer or step up to a 1:4 or 1:8 part like the 9DB803DFLFT (1:8, 400 MHz capable) or the 9DBL411BGLFT (1:4, LP-HCSL, 150 MHz). ## 0°C to 70°C — indoor equipment only The commercial temperature range (0°C to 70°C) limits this part to controlled environments: servers, switches, desktop PCs, test equipment, and telecom indoor racks. It is not rated for industrial motor drives, outdoor base stations, or automotive under-hood applications — those would need the -40°C to 85°C grade found on parts like the 9ZXL0851EKKLF. The active lifecycle status means no end-of-life risk for current designs; Renesas continues to manufacture this device in the 20-TSSOP package, and it is ROHS3 compliant with no exemption issues.","metaTitle":"9DB233AGLFT PCIe Clock Buffer, 110MHz, 1:2 Fanout, 20-TSSOP","metaDescription":"9DB233AGLFT PCIe Gen1/2/3 zero-delay clock buffer. 110MHz max, 1:2 HCSL fanout, 3.3V supply, 20-TSSOP. Active, ROHS3 compliant.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":"ROHS3 Compliant","productStatus":"Active","categoryPath":["Clock & Timing ICs"],"specifications":{"PLL":"Yes","Input":"Clock","Output":"HCSL","Package":"Tape & Reel (TR); Cut Tape (CT)","Main Purpose":"PCI Express (PCIe)","Mounting Type":"Surface Mount","Package / Case":"20-TSSOP (0.173\\\", 4.40mm Width)","Frequency - Max":"110MHz","lifecycle_stage":"eol_hot","Voltage - Supply":"3.135V ~ 3.465V","Number of Circuits":"1","Ratio - Input:Output":"1:2","Operating Temperature":"0°C ~ 70°C","Supplier Device Package":"20-TSSOP","Differential - Input:Output":"Yes/Yes"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$4.71","stockQuantity":0,"priceTiers":[{"qty":1,"price":"$4.71000","currency":"USD"},{"qty":10,"price":"$4.23100","currency":"USD"},{"qty":25,"price":"$3.99960","currency":"USD"},{"qty":100,"price":"$3.46630","currency":"USD"},{"qty":250,"price":"$3.28856","currency":"USD"},{"qty":500,"price":"$2.95082","currency":"USD"},{"qty":1000,"price":"$2.48864","currency":"USD"},{"qty":3000,"price":"$2.36421","currency":"USD"}]},"links":{"datasheetUrl":"https://cdn.icboms.com/36310344292effccc61640266f4db538.pdf","sourceUrl":null},"ai":{"faq":[{"question":"Is 9DB233AGLFT compatible with PCIe Gen3?","answer":"Yes. PCIe Gen3 uses a 100 MHz reference clock, and the 9DB233AGLFT supports frequencies up to 110 MHz with differential HCSL outputs — the standard signaling level for PCIe Gen1, Gen2, and Gen3 reference clocks. The PLL provides zero-delay buffering, so the output clock is phase-aligned to the input, which is required for Gen3 jitter budgets."},{"question":"Is 9DB233AGLFT RoHS compliant?","answer":"Yes, it is ROHS3 compliant, meeting the current RoHS directive without exemptions. This covers the 20-TSSOP package and all lead-free plating requirements for European and global markets."},{"question":"What is the difference between 9DB233AGLFT and 9DB231AGLFT?","answer":"The 9DB233AGLFT and 9DB231AGLFT are both Renesas PCIe zero-delay clock buffers in the same 20-TSSOP package, but they differ in fanout ratio. The 9DB233AGLFT provides a 1:2 input-to-output ratio (one input, two HCSL outputs), while the 9DB231AGLFT is a 1:1 buffer. Both operate from a 3.3 V supply and support up to 110 MHz. Choose the 9DB233AGLFT when you need to drive two downstream PCIe devices from one reference clock input."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/renesas/9DB233AGLFT","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/renesas/9DB233AGLFT when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-17T19:50:00.618Z","lastPublished":"2026-07-17T19:50:00.618Z","indexable":true}}