{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"74FCT16374ETPAG","brand":"Renesas Electronics","brandSlug":"renesas","productSlug":"74FCT16374ETPAG","canonicalUrl":"https://icboms.com/renesas/74FCT16374ETPAG","factsUrl":"https://icboms.com/api/mcp/products/74FCT16374ETPAG","rawCanonicalId":null},"summary":{"shortDescription":"Renesas Electronics 74FCT series D-Type flip-flop, 74FCT16374ETPAG, dual 8-bit, positive edge triggered, tri-state non-inverted outputs, 48-TSSOP surface mount package.","salesMarkdown":"## Dual 8-bit D-type in a 48-TSSOP footprint The 74FCT16374ETPAG is a dual 8-bit D-type flip-flop from Renesas Electronics, part of the 74FCT logic family. Each of the two elements stores eight bits, triggered on the positive edge of the clock, with tri-state non-inverted outputs that let multiple devices share a common bus without contention. The 3.7 ns max propagation delay at 5 V and 50 pF load sets the timing budget for high-speed address or data-path pipelines. Combined with 32 mA source and 64 mA sink output drive, this part can fan out to multiple loads on a backplane without external buffers. ## Supply, temperature, and package — the fit constraints Housed in a 48-TFSOP (0.240\", 6.10 mm width) package, also designated as 48-TSSOP in the supplier device package field. The 0.50 mm pitch fine-pitch TSSOP footprint is common for high-density logic; verify the PCB land pattern matches the 6.10 mm body width before committing the layout. Quiescent current is 500 µA typ, and input capacitance is 3.5 pF per pin — low enough that the clock-tree driver sees a light load even with all 16 inputs switching.","metaTitle":"Renesas 74FCT16374ETPAG D-Type Flip-Flop, 3.7ns, 48-TSSOP","metaDescription":"74FCT16374ETPAG dual 8-bit D-type flip-flop from Renesas. 3.7ns propagation delay at 5V, 32mA/64mA output drive. Active production, 48-TSSOP. Quoted to order.","metaKeywords":null},"attributes":{"series":"74FCT","packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["Microcontrollers & Processors (MCU / MPU / DSP)"],"specifications":{"Type":"D-Type","Series":"74FCT","Package":"Bulk","Function":"Standard","Output Type":"Tri-State, Non-Inverted","Trigger Type":"Positive Edge","Mounting Type":"Surface Mount","Package / Case":"48-TFSOP (0.240\\\", 6.10mm Width)","lifecycle_stage":"eol_hot","Voltage - Supply":"4.5V ~ 5.5V","Input Capacitance":"3.5 pF","Number of Elements":"2","Operating Temperature":"-40°C ~ 85°C (TA)","Supplier Device Package":"48-TSSOP","Current - Quiescent (Iq)":"500 µA","Current - Output High, Low":"32mA, 64mA","Number of Bits per Element":"8","Max Propagation Delay @ V, Max CL":"3.7ns @ 5V, 50pF"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$1.66","stockQuantity":18,"priceTiers":[{"qty":181,"price":"$1.66000","currency":"USD"}]},"links":{"datasheetUrl":"https://cdn.icboms.com/d33338b8d8c57d9f9354c26820d9fa59.pdf","sourceUrl":null},"ai":{"faq":[{"question":"What is the propagation delay of 74FCT16374ETPAG?","answer":"Maximum propagation delay is 3.7 ns at 5 V supply with a 50 pF load. This is the spec that governs timing closure in high-speed pipeline or bus-register applications."},{"question":"What package does 74FCT16374ETPAG come in?","answer":"It is supplied in a 48-TFSOP (0.240\", 6.10 mm width) surface-mount package, also referred to as 48-TSSOP. The 0.50 mm pitch requires a fine-pitch PCB land pattern."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/renesas/74FCT16374ETPAG","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/renesas/74FCT16374ETPAG when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-22T19:45:10.375Z","lastPublished":"2026-07-22T19:45:10.375Z","indexable":true}}