{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"74FCT16374CTPAG","brand":"Renesas Electronics","brandSlug":"renesas","productSlug":"74FCT16374CTPAG","canonicalUrl":"https://icboms.com/renesas/74FCT16374CTPAG","factsUrl":"https://icboms.com/api/mcp/products/74FCT16374CTPAG","rawCanonicalId":null},"summary":{"shortDescription":"Renesas 74FCT16374CTPAG, 74FCT series, D-Type flip-flop, dual 8-bit, tri-state non-inverted outputs, positive edge trigger, 4.5V to 5.5V supply, 5.2 ns propagation delay at 5V/50pF, industrial temp -40°C to 85°C, 48-TSSOP package.","salesMarkdown":"## Dual 8-bit D-type register for 5V bus applications The 74FCT16374CTPAG from Renesas (formerly IDT) is a dual 8-bit D-type flip-flop with tri-state, non-inverted outputs, packaged in a 48-TSSOP. It is designed for high-speed 5V bus interfaces where two independent 8-bit registers are needed on a single IC, each with its own clock and output enable. Key characteristics: positive edge-triggered on each of the two elements, each element holding 8 bits, with a max propagation delay of 5.2 ns at 5V and 50 pF load. Outputs source 32 mA and sink 64 mA, providing enough drive for heavily loaded backplanes or long traces. Operating temperature range is -40°C to 85°C, making it suitable for industrial environments such as factory automation, telecom racks, and motor drives where ambient temperatures can climb. ## 5.2 ns propagation delay — timing margin on a 5V bus At 5V and 50 pF load, the propagation delay is 5.2 ns max. The 32 mA / 64 mA output drive (high / low) is asymmetric: the low-side sink is double the high-side source. That is typical for CMOS outputs that drive capacitive loads; the falling edge will be faster than the rising edge. Account for that skew when matching trace lengths on a critical clock or data strobe. ## Package and footprint: 48-TSSOP The part is supplied in a 48-TSSOP package (body 6.10 mm wide). It is a surface-mount package. ## Lifecycle: active, no end-of-life concerns The 74FCT16374CTPAG is listed as Active in production. This part is suitable for new designs and ongoing production without obsolescence risk in the near term. The 74FCT series is a mature logic family with broad second-source availability across multiple manufacturers, though this specific suffix (CTPAG) is a Renesas/IDT ordering code.","metaTitle":"74FCT16374CTPAG D-Type Flip-Flop, 5.2 ns @ 5V, 48-TSSOP","metaDescription":"74FCT16374CTPAG dual 8-bit D-type flip-flop with tri-state outputs. 5.2 ns propagation delay at 5V, 50 pF. Industrial temp range -40°C to 85°C.","metaKeywords":null},"attributes":{"series":"74FCT","packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["DC-DC Power Modules"],"specifications":{"Type":"D-Type","Series":"74FCT","Package":"Bulk","Function":"Standard","Output Type":"Tri-State, Non-Inverted","Trigger Type":"Positive Edge","Mounting Type":"Surface Mount","Package / Case":"48-TFSOP (0.240\\\", 6.10mm Width)","lifecycle_stage":"eol_hot","Voltage - Supply":"4.5V ~ 5.5V","Input Capacitance":"3.5 pF","Number of Elements":"2","Operating Temperature":"-40°C ~ 85°C (TA)","Supplier Device Package":"48-TSSOP","Current - Quiescent (Iq)":"500 µA","Current - Output High, Low":"32mA, 64mA","Number of Bits per Element":"8","Max Propagation Delay @ V, Max CL":"5.2ns @ 5V, 50pF"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$1.13","stockQuantity":0,"priceTiers":[{"qty":265,"price":"$1.13000","currency":"USD"}]},"links":{"datasheetUrl":"https://cdn.icboms.com/d33338b8d8c57d9f9354c26820d9fa59.pdf","sourceUrl":null},"ai":{"faq":[{"question":"What is the propagation delay of 74FCT16374CTPAG?","answer":"Maximum propagation delay is 5.2 ns at 5V supply and 50 pF load. This is the clock-to-output delay for a single register element."},{"question":"What is the difference between 74FCT16374CTPAG and 74FCT16374CT?","answer":"The suffix 'PAG' indicates the 48-TSSOP package (TFSOP). The base part 74FCT16374CT is the same logic function but may be offered in other packages (e.g., SOIC, SSOP) or in die form. The 'PAG' variant is the surface-mount TSSOP version for compact board layouts."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/renesas/74FCT16374CTPAG","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/renesas/74FCT16374CTPAG when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-17T19:50:00.618Z","lastPublished":"2026-07-17T19:50:00.618Z","indexable":true}}