{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"74FCT162374ETPVG","brand":"Renesas Electronics","brandSlug":"renesas","productSlug":"74FCT162374ETPVG","canonicalUrl":"https://icboms.com/renesas/74FCT162374ETPVG","factsUrl":"https://icboms.com/api/mcp/products/74FCT162374ETPVG","rawCanonicalId":null},"summary":{"shortDescription":"Renesas Electronics 74FCT series D-Type flip-flop, 74FCT162374ETPVG, dual 8-bit, positive edge triggered, tri-state non-inverted outputs, 48-BSSOP, 4.5V-5.5V, -40°C to 85°C.","salesMarkdown":"## 3.7 ns propagation delay — what it means for bus timing The 74FCT162374ETPVG is a dual 8-bit D-type flip-flop from the 74FCT series, clocked on the positive edge with non-inverting tri-state outputs. Its 3.7 ns max propagation delay at 5 V and 50 pF load sets the data-to-output settling window — for a 50 MHz bus cycle (20 ns period), the output is valid within 18.5% of the cycle, leaving 16.3 ns for setup and hold at the receiver. This margin matters when the part sits in a fan-out buffer or pipeline register driving multiple loads. The 24 mA symmetrical output drive (both high and low) drives the specified 50 pF load without edge-rate degradation. On a heavily loaded backplane, the actual rise time depends on the total capacitance; the 3.5 pF input capacitance per channel keeps the loading on the driving stage low. The 500 µA quiescent current is the standby draw when all outputs are static — the dynamic current scales with the clock frequency and output load, not this figure. The 48-BSSOP package (7.50 mm body width) is a standard SSOP footprint — board layout matches the JEDEC MO-118 variation. ## Active lifecycle — no end-of-life concern Renesas lists the 74FCT162374ETPVG as Active — no PCN, no last-time-buy window, no successor to track.","metaTitle":"Renesas 74FCT162374ETPVG D-Type Flip-Flop, 3.7ns, 48-SSOP","metaDescription":"Renesas 74FCT162374ETPVG dual 8-bit D-type flip-flop with tri-state outputs. 3.7ns propagation delay at 5V, 50pF. Industrial temp range -40°C to 85°C.","metaKeywords":null},"attributes":{"series":"74FCT","packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["Analog & Data Acquisition"],"specifications":{"Type":"D-Type","Series":"74FCT","Package":"Bulk","Function":"Standard","Output Type":"Tri-State, Non-Inverted","Trigger Type":"Positive Edge","Mounting Type":"Surface Mount","Package / Case":"48-BSSOP (0.295\\\", 7.50mm Width)","lifecycle_stage":"eol_hot","Voltage - Supply":"4.5V ~ 5.5V","Input Capacitance":"3.5 pF","Number of Elements":"2","Operating Temperature":"-40°C ~ 85°C (TA)","Supplier Device Package":"48-SSOP","Current - Quiescent (Iq)":"500 µA","Current - Output High, Low":"24mA, 24mA","Number of Bits per Element":"8","Max Propagation Delay @ V, Max CL":"3.7ns @ 5V, 50pF"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$2.01","stockQuantity":0,"priceTiers":[{"qty":150,"price":"$2.01000","currency":"USD"}]},"links":{"datasheetUrl":"https://cdn.icboms.com/e6a72361bdcf6dca5d514c7e2b7ed360.pdf","sourceUrl":null},"ai":{"faq":[{"question":"What is the propagation delay of the 74FCT162374ETPVG?","answer":"This is the tPD from clock edge to data output valid — the spec that governs the maximum clock frequency in a synchronous bus design."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/renesas/74FCT162374ETPVG","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/renesas/74FCT162374ETPVG when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-08-11T15:49:49.435Z","lastPublished":"2026-08-11T15:49:49.435Z","indexable":true}}