{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"71V3556SA133BG","brand":"Renesas Electronics","brandSlug":"renesas","productSlug":"71V3556SA133BG","canonicalUrl":"https://icboms.com/renesas/71V3556SA133BG","factsUrl":"https://icboms.com/api/mcp/products/71V3556SA133BG","rawCanonicalId":null},"summary":{"shortDescription":"Renesas 71V3556SA133BG, Synchronous SRAM (ZBT), 4.5 Mbit (128K x 36), 133 MHz clock, 4.2 ns access, Parallel interface, 3.135V–3.465V supply, 0°C–70°C, 119-PBGA (14x22 mm).","salesMarkdown":"## Synchronous ZBT SRAM at 133 MHz — what the pipeline buys you The Renesas 71V3556SA133BG is a 4.5 Mbit synchronous SRAM organized 128K x 36, using a Zero Bus Turnaround (ZBT) architecture that eliminates the dead cycle when switching between read and write. It clocks at 133 MHz with a 4.2 ns access time from the clock edge, which means back-to-back transactions at full bus rate with no wait-state insertion for direction changes. The 36-bit word width maps naturally to a 32-bit data bus plus parity or ECC lane, common in network packet buffers, DSP ping-pong memories, and high-speed cache applications. ## Timing margin and the 4.2 ns access window At 133 MHz the clock period is 7.5 ns. The 4.2 ns access time leaves about 3.3 ns for the controller to capture data before the next clock edge. That budget covers PCB trace delay, input capacitance, and setup time of the receiving FPGA or ASIC. If the design uses a 133 MHz memory controller, verify the input setup requirement against this window — a 3.3 ns margin is comfortable for short traces on a moderate-density board, but a heavily loaded bus or long routing may force a speed-grade bump or a slower clock. The ZBT pipeline adds one cycle of latency on the first access, but subsequent pipelined reads and writes sustain full throughput. ## Package and supply rail — footprint and decoupling notes The 119-ball PBGA measures 14x22 mm, a standard fine-pitch BGA footprint. Decoupling should follow the manufacturer's recommended capacitor placement — multiple 0.1 µF ceramics distributed near the supply balls, plus a bulk capacitor per the layout guide. For extended temperature or industrial use, check the -I or -B temperature grade variants in the family. ## Active lifecycle — no imminent EOL, suitable for production For dual-sourcing or drop-in replacement, the 71V3556SA133BG is a standard density and speed grade in the 71V3556 family; other speed grades (e.g., 100 MHz or 166 MHz) share the same 119-PBGA footprint and pinout, allowing a speed upgrade without a board respin.","metaTitle":"71V3556SA133BG SRAM, 4.5 Mbit, 133 MHz, 4.2 ns, 119-PBGA","metaDescription":"71V3556SA133BG synchronous ZBT SRAM from Renesas: 4.5 Mbit (128K x 36), 133 MHz clock, 4.2 ns access, 119-PBGA. Active lifecycle.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":null,"productStatus":"Active","categoryPath":["Logic ICs"],"specifications":{"Package":"Bulk","Technology":"SRAM - Synchronous, SDR (ZBT)","Access Time":"4.2 ns","Memory Size":"4.5Mbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"119-BGA","Clock Frequency":"133 MHz","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"3.135V ~ 3.465V","Memory Organization":"128K x 36","Operating Temperature":"0°C ~ 70°C (TA)","Supplier Device Package":"119-PBGA (14x22)"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$5.46","stockQuantity":0,"priceTiers":[{"qty":55,"price":"$5.46000","currency":"USD"}]},"links":{"datasheetUrl":"https://cdn.icboms.com/f215e63550592a192ce1bb04318c59ff.pdf","sourceUrl":null},"ai":{"faq":[{"question":"Is the 71V3556SA133BG obsolete or end-of-life?","answer":"No. Renesas continues to manufacture this part; no EOL or last-time-buy has been announced."},{"question":"What is the memory organization and clock speed of the 71V3556SA133BG?","answer":"It is organized 128K x 36 (4.5 Mbit total) and operates at a 133 MHz clock frequency with a 4.2 ns access time. The ZBT pipeline allows zero dead cycles when switching between read and write."},{"question":"Does the 71V3556SA133BG require external termination resistors?","answer":"The datasheet specifies a synchronous ZBT interface with standard CMOS I/O levels. For signal integrity on longer traces or higher bus loads, series termination resistors at the driver end are recommended per the controller's guidelines, but the SRAM itself does not require on-die termination."},{"question":"What is the closest pin-compatible alternative to the 71V3556SA133BG?","answer":"Other speed grades in the same 71V3556 family (e.g., 100 MHz or 166 MHz versions) share the same 119-PBGA footprint and pinout, allowing a speed upgrade or downgrade without a PCB change. For a different density, the 71V3576 family (9 Mbit) uses a different pinout and is not drop-in compatible."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/renesas/71V3556SA133BG","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/renesas/71V3556SA133BG when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-17T19:50:00.618Z","lastPublished":"2026-07-17T19:50:00.618Z","indexable":true}}