{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"7143LA20JG","brand":"Renesas Electronics","brandSlug":"renesas","productSlug":"7143LA20JG","canonicalUrl":"https://icboms.com/renesas/7143LA20JG","factsUrl":"https://icboms.com/api/mcp/products/7143LA20JG","rawCanonicalId":null},"summary":{"shortDescription":"Renesas 7143LA20JG, SRAM - Dual Port, Asynchronous, 32 Kbit (2K x 16), Parallel interface, 20 ns access time, 4.5V ~ 5.5V supply, 0°C ~ 70°C, 68-PLCC (J-Lead), Tube.","salesMarkdown":"## Dual-port asynchronous SRAM — 32 Kbit, 20 ns, 5 V The Renesas 7143LA20JG is a 32 Kbit dual-port asynchronous SRAM organised as 2K × 16 bits, with a 20 ns access time and a 4.5 V to 5.5 V supply range. It is built for applications where two independent buses — typically a DSP and a microcontroller, or two processors — need simultaneous read/write access to a shared memory block without external arbitration logic. The 16-bit word width maps directly onto a 16-bit data bus, saving byte-lane multiplexing. The part is rated for commercial temperature environments (0°C to 70°C) and comes in a 68-lead PLCC with J-leads, a surface-mount footprint common in mid-1990s through 2000s designs. ## 20 ns access time — bus timing margin The 20 ns access time is the time from address valid to data valid on a read cycle. The write cycle time is also 20 ns. ## Temperature grade and environment The 0°C to 70°C operating temperature range limits this part to commercial/indoor equipment. It is not rated for industrial environments. ## Package and footprint The 68-PLCC package (24.21 × 24.21 mm body) uses J-leads. It is a surface-mount package that can be soldered directly or socketed. ## Lifecycle and sourcing The 7143LA20JG is listed as Active and ROHS3 compliant. There is no last-time-buy notice or end-of-life indication. The part is available through independent distribution and can be quoted to order. For BOM planning, there is no immediate obsolescence risk, but dual-port SRAMs are a shrinking market — most new designs migrate to dual-port RAM in FPGAs or to QDR/DDR SRAM. If the design is locked to this footprint, confirm supply annually.","metaTitle":"7143LA20JG SRAM Dual-Port Asynchronous, 32 Kbit, 20 ns","metaDescription":"7143LA20JG 32 Kbit (2K x 16) dual-port asynchronous SRAM with 20 ns access time, 4.5V-5.5V supply, 0°C-70°C, 68-PLCC. Active lifecycle, ROHS3 compliant.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":"ROHS3 Compliant","productStatus":"Active","categoryPath":["Analog & Data Acquisition"],"specifications":{"Package":"Tube","Technology":"SRAM - Dual Port, Asynchronous","Access Time":"20 ns","Memory Size":"32Kbit","Memory Type":"Volatile","Memory Format":"SRAM","Mounting Type":"Surface Mount","Package / Case":"68-LCC (J-Lead)","lifecycle_stage":"eol_hot","Memory Interface":"Parallel","Voltage - Supply":"4.5V ~ 5.5V","Memory Organization":"2K x 16","Operating Temperature":"0°C ~ 70°C (TA)","Supplier Device Package":"68-PLCC (24.21x24.21)","Write Cycle Time - Word, Page":"20ns"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$36.7","stockQuantity":0,"priceTiers":[{"qty":1,"price":"$36.70000","currency":"USD"},{"qty":10,"price":"$34.03500","currency":"USD"},{"qty":25,"price":"$32.81960","currency":"USD"},{"qty":50,"price":"$32.00220","currency":"USD"},{"qty":100,"price":"$28.04110","currency":"USD"},{"qty":250,"price":"$27.26572","currency":"USD"}]},"links":{"datasheetUrl":"https://cdn.icboms.com/71ca09395008186ee3222094ae02b099.pdf","sourceUrl":null},"ai":{"faq":[{"question":"What is the access time of 7143LA20JG?","answer":"The access time is 20 ns for both read and write cycles. The write cycle time — word, page — is also 20 ns."},{"question":"Can 7143LA20JG be used in industrial temperature applications?","answer":"No. The operating temperature range is 0°C to 70°C (commercial grade). It is not rated for -40°C to 85°C industrial environments."},{"question":"What is the difference between 7143LA20JG and 7143LA25JG?","answer":"The only difference is access time: 7143LA20JG is 20 ns, while 7143LA25JG is 25 ns. All other specifications — density, organisation, supply voltage, package, temperature range — are identical. The 20 ns part gives tighter bus timing margin at the same clock rate."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/renesas/7143LA20JG","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/renesas/7143LA20JG when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-13T23:23:34.781Z","lastPublished":"2026-07-13T23:23:34.781Z","indexable":true}}