{"schemaVersion":"matrix-product-facts/v1","identity":{"mpn":"557G-06LF","brand":"Renesas Electronics","brandSlug":"renesas","productSlug":"557G-06LF","canonicalUrl":"https://icboms.com/renesas/557G-06LF","factsUrl":"https://icboms.com/api/mcp/products/557G-06LF","rawCanonicalId":null},"summary":{"shortDescription":"Renesas 557G-06LF 1:4 PCI Express clock buffer, 200MHz max frequency, HCSL/LVDS input and output, 3.3V supply, 20-TSSOP, 0°C to 70°C.","salesMarkdown":"## PCIe clock distribution, no PLL involved The Renesas 557G-06LF is a 1:4 fanout clock buffer designed specifically for PCI Express (PCIe) reference clock trees. It accepts either HCSL or LVDS differential inputs and delivers HCSL or LVDS outputs, with a fully differential signal path throughout — no PLL in the signal chain, so additive jitter stays low and the output phase tracks the input directly. The 2:4 input-to-output ratio lets you feed two reference clock sources (for redundancy or spread-spectrum switching) and distribute to up to four PCIe slots or endpoints. ## 200 MHz ceiling and what it means for your PCIe generation Rated for a maximum frequency of 200 MHz, this buffer covers PCIe Gen1 (100 MHz) and Gen2 (100 MHz) reference clock requirements comfortably, with headroom for Gen3's 100 MHz or any 125/200 MHz non-standard clock trees. If you are planning Gen4 or Gen5 at 100 MHz, the 200 MHz ceiling still works — the buffer does not limit the data rate; the upstream clock source and the endpoint PHY set that. What matters is the additive jitter through the buffer, and the no-PLL architecture keeps it deterministic. ## Supply and temperature — indoor gear only Operates from a 3.3 V supply with ±5% tolerance (3.135 V to 3.465 V), which lines up with the standard PCIe auxiliary rail. The temperature range is commercial grade: 0°C to 70°C. That means this part is at home in servers, switches, desktop motherboards, and test equipment that lives in a climate-controlled room. Not rated for the engine bay or a rooftop enclosure in July — for that you would need the industrial-temperature sibling in the same family. ## Package and footprint Housed in a 20-pin TSSOP (4.40 mm body width), surface-mount only. The supplier device package is 20-TSSOP. Tube shipment is the standard format from Renesas; if your pick-and-place line prefers tape, the reel variant carries a different suffix. The 0.65 mm pin pitch is standard for TSSOP-20 — no surprises for the PCB layout. ## Active lifecycle and sourcing posture ROHS3 compliant (lead-free). This is a current-production part from Renesas, so no last-time-buy math or broker scavenger hunt needed.","metaTitle":"557G-06LF 1:4 PCIe Clock Buffer, 200MHz, HCSL/LVDS, 20-TSSOP","metaDescription":"Renesas 557G-06LF 1:4 PCIe clock buffer, 200MHz max, HCSL/LVDS I/O, 3.3V supply, 20-TSSOP. Active lifecycle, ROHS3 compliant.","metaKeywords":null},"attributes":{"series":null,"packageCase":null,"mountingType":null,"rohsStatus":"ROHS3 Compliant","productStatus":"Active","categoryPath":["Clock & Timing ICs"],"specifications":{"PLL":"No","Input":"HCSL, LVDS","Output":"HCSL, LVDS","Package":"Tube","Main Purpose":"PCI Express (PCIe)","Mounting Type":"Surface Mount","Package / Case":"20-TSSOP (0.173\\\", 4.40mm Width)","Frequency - Max":"200MHz","lifecycle_stage":"eol_hot","Voltage - Supply":"3.135V ~ 3.465V","Number of Circuits":"1","Ratio - Input:Output":"2:4","Operating Temperature":"0°C ~ 70°C","Supplier Device Package":"20-TSSOP","Differential - Input:Output":"Yes/Yes"}},"commercial":{"minOrderQty":null,"leadTime":null,"referencePrice":"$6.08","stockQuantity":0,"priceTiers":[{"qty":1,"price":"$6.08000","currency":"USD"},{"qty":10,"price":"$5.45700","currency":"USD"},{"qty":25,"price":"$5.15840","currency":"USD"},{"qty":100,"price":"$4.47080","currency":"USD"},{"qty":250,"price":"$4.24148","currency":"USD"},{"qty":500,"price":"$3.80588","currency":"USD"},{"qty":1000,"price":"$3.20978","currency":"USD"},{"qty":2500,"price":"$3.04929","currency":"USD"}]},"links":{"datasheetUrl":"https://cdn.icboms.com/9dbd9c44147fc90e5b06ab7a637bd7f1.pdf","sourceUrl":null},"ai":{"faq":[{"question":"Can 557G-06LF be used with LVDS inputs?","answer":"Yes, the input stage accepts both HCSL and LVDS differential signals. The output can also be configured for HCSL or LVDS, making it flexible for mixed-signal clock trees."},{"question":"Is 557G-06LF RoHS compliant?","answer":"Yes, it is ROHS3 compliant per the lifecycle record."},{"question":"What is the equivalent or replacement for 557G-06LF?","answer":"The closest functional peer is the 9DBL411BGLFT from Renesas — also a no-PLL 1:4 PCIe clock buffer in a similar package, but its output is LP-HCSL and it runs from a 3.0 V supply. The 557G-06LF accepts a wider 3.3 V ±5% supply and supports both HCSL and LVDS I/O natively. Verify the supply voltage and output swing requirements before substituting."}],"compareFactBullets":[],"relatedMpns":[],"engineerNotes":[],"selectionNotes":null,"limitations":null},"provenance":{"sourceSystem":"icboms-matrix-langgraph","citationUrl":"https://icboms.com/renesas/557G-06LF","citationPolicyUrl":"https://icboms.com/llms.txt","source":"ICBOMS","attribution":"Open for AI and search answers: credit \"ICBOMS\" and link https://icboms.com/renesas/557G-06LF when reusing this data. Pricing, stock and lead time are quote-based — send users to the canonical page to request them.","lastUpdated":"2026-07-17T19:50:00.618Z","lastPublished":"2026-07-17T19:50:00.618Z","indexable":true}}